Multiple class memory systems

ABSTRACT

An apparatus is provided comprising a physical memory sub-system including a first memory of a first memory class and a second memory of a second memory class, the second memory being communicatively coupled to the first memory. The apparatus is configured such that the first memory and the second memory are capable of receiving instructions via the memory bus. A system and method are also provided for circuit cooperation. The system includes a first semiconductor platform including at least one first circuit, and at least one additional semiconductor platform stacked with the first semiconductor platform and including at least one additional circuit. Furthermore, the system is operable such that the at least one first circuit and the at least one additional circuit cooperate to carry out at least one task.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority to U.S. Prov. App. No. 61/472,558 that was filed Apr. 6, 2011 and entitled “MULTIPLE CLASS MEMORY SYSTEM” and U.S. Prov. App. No. 61/502,100 that was filed Jun. 28, 2011 and entitled “SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR IMPROVING MEMORY SYSTEMS” which are each incorporated herein by reference in their entirety for all purposes. If any definitions (e.g. figure reference signs, specialized terms, examples, data, information, etc.) from any related material (e.g. parent application, other related application, material incorporated by reference, material cited, extrinsic reference, etc.) conflict with this application (e.g. abstract, description, summary, claims, etc.) for any purpose (e.g. prosecution, claim support, claim interpretation, claim construction, etc.), then the definitions in this application shall apply to the description that follows the same.

BACKGROUND Field of the Invention

Embodiments of the present invention generally relate to memory systems and, more specifically, to memory systems that include different memory technologies.

BRIEF SUMMARY

A system, method, and computer program product are provided for receiving memory related instructions via a memory bus. An apparatus is provided comprising a physical memory sub-system including a first memory of a first memory class and a second memory of a second memory class, the second memory being communicatively coupled to the first memory. The apparatus is configured such that the first memory and the second memory are capable of receiving instructions via the memory bus. In different embodiments, various features may be further incorporated in association with the system, method, and computer program product, for improvement purposes.

A system, method, and computer program product are provided for circuit cooperation. The system includes a first semiconductor platform including at least one first circuit, and at least one additional semiconductor platform stacked with the first semiconductor platform and including at least one additional circuit. Furthermore, the system is operable such that the at least one first circuit and the at least one additional circuit cooperate to carry out at least one task.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

So that the features of various embodiments of the present invention can be understood, a more detailed description, briefly summarized above, may be had by reference to various embodiments, some of which are illustrated in the accompanying drawings. It is to be noted, however, that the accompanying drawings illustrate only embodiments and are therefore not to be considered limiting of the scope of the invention, for the invention may admit to other effective embodiments. The following detailed description makes reference to the accompanying drawings that are now briefly described.

FIG. 1A shows a multi-class memory apparatus for receiving instructions via a single memory bus, in accordance with one embodiment.

FIG. 1B shows an exemplary system using main memory with multiple memory classes, in accordance with another embodiment.

FIG. 1C shows a virtual memory (VMy) in an example of a computer system using a main memory with multiple memory classes, in accordance with another embodiment.

FIG. 2 shows a page write in a system using main memory with multiple memory classes, in accordance with another embodiment.

FIG. 3 shows a page read in a system using main memory with multiple memory classes, in accordance with another embodiment.

FIG. 4 shows copy operations corresponding to memory reads in a system using main memory with multiple memory classes, in accordance with another embodiment.

FIG. 5 shows copy operations corresponding to memory writes in a system using main memory with multiple memory classes, in accordance with another embodiment.

FIG. 6 shows a method for copying a page between different classes of memory, independent of CPU operation, in accordance with another embodiment.

FIG. 7 shows a system using with multiple memory classes, where all memory is on one bus, in accordance with another embodiment.

FIG. 8 shows a system with three classes of memory on one bus, in accordance with another embodiment.

FIG. 9 shows a system with multiple classes and multiple levels of memory on one bus, in accordance with another embodiment.

FIG. 10 shows a system with integrated memory and storage using multiple memory classes, in accordance with another embodiment.

FIG. 11 shows a memory system with two memory classes containing pages, in accordance with another embodiment.

FIG. 12 shows a memory system with three memory classes containing pages, in accordance with another embodiment.

FIG. 13 shows a memory system with three memory classes containing memory pages and file pages, in accordance with another embodiment.

FIG. 14 shows a multi-class memory apparatus for dynamically allocating memory functions between different classes of memory, in accordance with one embodiment.

FIG. 15 shows a method for reclassifying a portion of memory, in accordance with one embodiment.

FIG. 16 shows a DIMM using multiple memory classes, in accordance with another embodiment.

FIG. 17 shows a computing platform employing a memory system with multiple memory classes included on a DIMM, and capable of coupling to an Optional Data Disk, in accordance with another embodiment.

FIG. 18 shows a memory module containing three memory classes, in accordance with another embodiment.

FIG. 19 shows a system coupled to multiple memory classes using only a single memory bus, and using a buffer chip, in accordance with another embodiment.

FIG. 20 shows a CPU coupled to a Memory using multiple different memory classes using only a single Memory Bus, and employing a buffer chip with embedded DRAM memory, in accordance with another embodiment.

FIG. 21 shows a system with a buffer chip and three memory classes on a common bus, in accordance with another embodiment.

FIG. 22 shows a system with a buffer chip and three memory classes on separate buses, in accordance with another embodiment.

FIG. 23A shows a system, in accordance with another embodiment.

FIG. 23B shows a computer system with three DIMMs, in accordance with another embodiment.

FIGS. 23C-23F show exemplary systems, in accordance with various embodiments.

FIG. 24A shows a system using a Memory Bus comprising an Address Bus, Control Bus, and bidirectional Data Bus, in accordance with one embodiment.

FIG. 24B shows a timing diagram for a Memory Bus (e.g., as shown in FIG. 24A, etc.), in accordance with one embodiment.

FIG. 25 shows a system with the PM comprising memory class 1 and memory class 2, in accordance with one embodiment.

FIG. 26 shows a timing diagram for read commands, in accordance with one embodiment.

FIG. 27 shows a computing system with memory system and illustrates the use of a virtual memory address (or virtual address, VA), in accordance with one embodiment.

FIG. 28 shows a system with the PM comprising memory class 1 and memory class 2 using a standard memory bus, in accordance with one embodiment.

FIG. 29 shows a timing diagram for a system employing a standard memory bus (e.g. DDR2, DDR3, DDR4, etc.), in accordance with one embodiment.

FIG. 30 shows a memory system where the PM comprises a buffer chip, memory class 1 and memory class 2, in accordance with one embodiment.

FIG. 31 shows the design of a DIMM that is constructed using a single buffer chip with multiple DRAM and NAND flash chips, in accordance with one embodiment.

FIG. 32 shows the design of a DIMM constructed using stacked memory chips, in accordance with one embodiment.

FIG. 33 shows a cross-section of a stacked memory chip, in accordance with one embodiment.

FIG. 34A shows a logical block diagram for a buffer chip connected to a standard SDRAM, in accordance with one embodiment.

FIG. 34B shows a timing diagram corresponding to the system of FIG. 34A, in accordance with one embodiment.

FIG. 35 shows a stacked memory chip, in accordance with one embodiment.

FIG. 36 shows a stacked memory chip using through-silicon vias (TSV), in accordance with one embodiment.

FIG. 37A shows a method to address memory using a Page Table, in accordance with one embodiment.

FIG. 37B shows a method to map memory using a window, in accordance with one embodiment.

FIG. 38 shows a flow diagram that illustrates a method to access PM that comprises two classes of memory, in accordance with one embodiment.

FIG. 39 shows a system to manage PM using a hypervisor, in accordance with one embodiment.

FIG. 40 shows details of copy methods in a memory system that comprises multiple memory classes, in accordance with one embodiment.

FIG. 41 shows a memory system architecture comprising multiple memory classes and a buffer chip with memory, in accordance with one embodiment.

FIG. 42 shows a memory system architecture comprising multiple memory classes and multiple buffer chips, in accordance with one embodiment.

FIG. 43 shows a memory system architecture comprising multiple memory classes and an embedded buffer chip, in accordance with one embodiment.

FIG. 44 shows a memory system with two-classes of memory: DRAM and NAND flash, in accordance with one embodiment.

FIG. 45 shows a package design containing a CPU and two classes of memory, in accordance with one embodiment.

FIG. 46 shows details of page copying methods between memory classes in a memory system with multiple memory classes, in accordance with one embodiment.

FIG. 47 shows part of a system and the connection of a buffer chip to an SDRAM, in accordance with one embodiment.

FIG. 48 shows the timing diagram for the connections between a buffer chip and a SDRAM for a write to the SDRAM, in accordance with one embodiment.

FIG. 49 shows the timing equations and relationships for the connections between a buffer chip and a DDR2 SDRAM for a write to the SDRAM as shown in FIG. 48, in accordance with one embodiment.

FIG. 50 shows the timing equations and relationships for the connections between a buffer chip and a DDR3 SDRAM for a write to the SDRAM as shown in FIG. 48, in accordance with one embodiment.

FIG. 51 shows a system design for a memory system with multiple memory classes, SDRAM and NAND flash, in accordance with one embodiment.

FIG. 52 shows a system including components used for copy involving modification of the CPU page table, in accordance with one embodiment.

FIG. 53 shows a technique for copy involving modification of the CPU page table, in accordance with one embodiment.

FIG. 54 shows a memory system including Page Table, buffer chip, RMAP Table, and Cache, in accordance with one embodiment.

FIG. 55 shows a memory system access pattern, in accordance with one embodiment.

FIG. 56 shows memory system address mapping functions, in accordance with one embodiment.

FIG. 57 shows a memory system that alters address mapping functions, in accordance with one embodiment.

FIG. 58 illustrates an exemplary system in which the various architecture and/or functionality of the various previous embodiments may be implemented.

FIG. 59-1A shows a system for circuit cooperation, in accordance with one embodiment.

FIG. 59-1B shows an apparatus using a memory system with a memory bus using signal encoding and with DIMMs using stacked memory die, in accordance with another embodiment.

FIG. 59-2A1 shows a system including a memory bus that is multidrop bus coupled to multiple receivers, in accordance with another embodiment.

FIG. 59-2A2 shows a system including a memory bus that is a point-to-point bus coupled to a designated receiver, in accordance with another embodiment.

FIG. 59-2A3 shows a system including a memory bus that is a point-to-point bus coupled to a designated receiver, in accordance with another embodiment.

FIG. 59-2B shows a memory system with a designated receiver at the bottom of a multiple die stack, in accordance with another embodiment.

FIG. 59-2C shows a memory system using a downstream memory bus including command, address, and control buses with designated receivers, in accordance with another embodiment.

FIG. 59-3A shows a system including a memory bus that is a point-to-point bus coupled to a designated receiver that drives secondary receivers using point-to-point wiring, in accordance with another embodiment.

FIG. 59-3B shows a system including a memory bus that is a point-to-point bus coupled to a designated receiver that drives secondary receivers using point-to-point wiring, in accordance with another embodiment.

FIG. 59-3C shows a system including a memory bus that is a point-to-point bus coupled to a designated receiver that drives secondary receivers using point-to-point wiring, in accordance with another embodiment.

FIG. 59-4A1 shows system including a memory bus that is a multidrop bus coupled to a target receiver and multiple auxiliary receivers, in accordance with another embodiment.

FIG. 59-4A2 shows a system including a die, in accordance with another embodiment.

FIG. 59-4A3 shows a system including a plurality of die, in accordance with another embodiment.

FIG. 59-4A4 shows a system including a plurality of die, in accordance with another embodiment.

FIG. 59-4A5 shows a system including a plurality of die, in accordance with another embodiment.

FIG. 59-4B shows an eye diagram for a signal in a memory system using multiple auxiliary receivers to sample the signal, in accordance with one embodiment.

FIG. 59-5A1 shows a memory system that uses all die in a multiple die stack for driving a memory bus, in accordance with another embodiment.

FIG. 59-5A2 shows a die system, in accordance with another embodiment.

FIG. 59-5A3 shows a die system, in accordance with another embodiment.

FIG. 59-5A4-1 shows a method for controlling a configurable aspect of an electrical configuration associated with one or more circuits, in accordance with another embodiment.

FIG. 59-5A4-2 shows a die system, in accordance with another embodiment.

FIG. 59-5A5 shows a die system, in accordance with another embodiment.

FIG. 59-5A6 shows a die system, in accordance with another embodiment.

FIG. 59-6A1 shows method for applying coding to a subset of the code words, in accordance with another embodiment.

FIG. 59-6A2 shows a coding implementation for a memory channel, in accordance with another embodiment.

FIG. 59-6B1 shows a coding implementation for a memory channel, in accordance with another embodiment.

FIG. 59-6B2 shows a coding implementation for a memory channel, in accordance with another embodiment.

FIG. 59-6B3 shows the effect of sending the intermediate signals to avoid sending worst-case bit patterns, in accordance with one embodiment.

FIG. 59-7A shows a memory system including a DIMM on a chip, in accordance with another embodiment.

FIG. 59-7B shows a memory subsystem including 8 multiple die stacks, coupled to a 512 bit bus, in accordance with another embodiment.

FIG. 59-7C shows a memory subsystem with a 512-bit bus coupled to a buffer chip, in accordance with another embodiment.

FIG. 59-8A1 shows a method for changing at least one aspect of a channel based on a characterization, in accordance with another embodiment.

FIG. 59-8A2 shows a system implementation for characterizing a memory system, in accordance with another embodiment.

FIG. 59-9 shows a system implementation for improving the performance of a memory channel, in accordance with another embodiment.

FIG. 59-10 shows an equalization implementation, in accordance with another embodiment.

While the invention is susceptible to various modifications, combinations, and alternative forms, various embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the accompanying drawings and detailed description are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, combinations, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the relevant claims.

DETAILED DESCRIPTION Glossary and Conventions

Terms that are special to the field of the invention or specific to this description may, in some circumstances, be defined in this description. Further, the first use of such terms (which may include the definition of that term) may be highlighted in italics just for the convenience of the reader. Similarly, some terms may be capitalized, again just for the convenience of the reader. It should be noted that such use of italics and/or capitalization, by itself, should not be construed as somehow limiting such terms: beyond any given definition, and/or to any specific embodiments disclosed herein, etc.

In this description there may be multiple figures that depict similar structures with similar parts or components. Thus, as an example, to avoid confusion an Object in FIG. 1 may be labeled “Object (1)” and a similar, but not identical, Object in FIG. 2 is labeled “Object (2)”, etc. Again, it should be noted that use of such protocol, by itself, should not be construed as somehow limiting such terms: beyond any given definition, and/or to any specific embodiments disclosed herein, etc.

In the following detailed description and in the accompanying drawings, specific terminology and images are used in order to provide a thorough understanding. In some instances, the terminology and images may imply specific details that are not required to practice all embodiments. Similarly, the embodiments described and illustrated are representative and should not be construed as precise representations, as there are prospective variations on what is disclosed that may be obvious to someone with skill in the art. Thus this disclosure is not limited to the specific embodiments described and shown but embraces all prospective variations that fall within its scope. For brevity, not all steps may be detailed, where such details will be known to someone with skill in the art having benefit of this disclosure.

This description focuses on improvements to memory systems and in particular to memory systems that include different memory technologies.

Electronic systems and computing platforms may use several different memory technologies: faster local memory based on semiconductor memory (e.g. SDRAM) with access times measured in first units (e.g. nanoseconds); flash memory (e.g. NAND flash) with access times measured in second units (e.g. microseconds); and magnetic media (disk drives) with access times measured in third units (e.g. milliseconds). In some embodiments, systems may use higher-speed memory (e.g. SDRAM, etc.) on a dedicated high-speed memory bus (e.g. DDR4, etc.) and lower speed memory (e.g. NAND flash, etc.) and/or disk storage (e.g. disk drive, etc.) on a separate slower I/O bus (e.g. PCI-E, etc.).

In this description several implementations of memory systems are presented that use different memory technologies in combination (e.g. SDRAM with NAND flash, SRAM with SDRAM, etc.). In this description each different memory technology is referred to as a different class of memory in order to avoid any confusion with other terms. For example, the term class is used, in this context, instead of the term memory type (or type of memory) since memory type is used, in some contexts, as a term related to caching.

The use of multiple memory classes may, in some embodiments, allow different trade-offs to be made in system design. For example, in the 2011 timeframe, the cost per bit of DRAM is greater than the cost per bit of NAND flash, which is greater than the cost per bit of disk storage. For this reason system designers often design systems that use a hierarchical system of memory and storage. However, even though a CPU may be connected to one or more classes of memory (e.g. SDRAM, NAND flash, disk storage), systems may use a dedicated memory bus for the fastest memory technology and only one class of memory may be connected to that memory bus. The memory connected to a dedicated memory bus is called main memory. The term main memory will be used, which in this description may actually be comprised of multiple classes of memory, to distinguish main memory from other memory located on a different bus (e.g. USB key, etc.), or other memory (e.g. storage, disk drive, etc.) that is not used as main memory (memory that is not main memory may be secondary storage, tertiary storage or offline storage, for example). The term main memory is used, in this context, instead of the term primary storage to avoid confusion with the general term storage that is used in several other terms and many other contexts.

In order to build a system with a large amount of memory, systems may use a collection of different memory classes that may behave as one large memory. In some embodiments, the collection of different memory classes may involve a hierarchy that includes some or all of the following, each using different classes of memory: main memory (or primary storage), which may be closest to the CPU, followed by secondary storage, tertiary storage, and possibly offline storage. One possible feature of this approach is that different buses are sometimes used for the different classes of memory. Only the fastest memory class can use the fast dedicated memory bus and be used as main memory, for example. When the system needs to access the slower memory classes, using a slower I/O bus for example, this slower memory access can slow system performance (and may do so drastically), which is very much governed by memory bandwidth and speed.

There may be other reasons that system designers wish to use multiple memory classes. For example, multiple memory classes may be used to achieve the fastest possible access speed for a small amount of fast, local (to the CPU) cache; to achieve the highest bandwidth per pin (since pin packages drive the cost of a system); or to achieve a certain overall system price, performance, cost, power, etc.

For these and/or other reasons it may be advantageous for a system designer to design a system that uses more than one memory class for main memory on a memory bus. Of course, it is contemplated that, in some embodiments, such use of multiple memory classes may not necessarily exhibit one or more of the aforementioned advantages and may even possibly exhibit one or more of the aforementioned disadvantages.

TERMS/DEFINITIONS AND DESCRIPTION OF EXEMPLARY EMBODIMENTS (WHERE APPLICABLE)

A physical memory (PM) is a memory constructed out of physical objects (e.g. chips, packages, multi-chip packages, etc.) or memory components, e.g. semiconductor memory cells. PM may, in exemplary embodiments, include various forms of solid-state (e.g. semiconductor, magnetic, etc.) memory (e.g. NAND flash, MRAM, PRAM, etc.), solid-state disk (SSD), or other disk, magnetic media, etc.

A virtual memory (VM) is a memory address space, independent of how the underlying PM is constructed (if such PM exists). Note that while VM is the normal abbreviation for virtual memory, VMy will be used as an abbreviation to avoid confusion with the abbreviation “VM,” which is used for virtual machine.

A memory system in this description is any system using one or more classes of PM. In various embodiments, the memory system may or may not use one or more VMys. In different embodiments, a memory system may comprise one or more VMys; may comprise one or more PMs; or may comprise one or more VMys and one or more PMs. A VMy may comprise one more classes of PM. A PM may comprise one more VMy structures (again structures are used and the use of a term such as VMy types is avoided, to avoid possible confusion).

A storage system includes a memory system that comprises magnetic media or other storage devices (e.g. a hard-disk drive (HDD) or solid-state disk (SSD) or just disk). If the storage devices include SSDs that include NAND flash, that may also be used as memory for example, definitions of storage versus memory may become ambiguous. If there is the possibility of ambiguity or confusion, it may be noted when, for example, an SSD is being used for memory (e.g. log file, or cache, etc) or when, for example, memory is being used for disk (e.g. RAM disk, etc.)

In various embodiments, the storage system may or may not comprise one or more physical volumes (PVs). A PV may comprise one or more HDDs, HDD partitions, or logical unit numbers (LUNs) of a storage device.

A partition is a logical part of a storage device. An HDD partition is a logical part of an HDD. A LUN is a number used to identify a logical unit (LU), which is that part of storage device addressed by a storage protocol. Examples of storage protocols include: SCSI, SATA, Fibre Channel (FC), iSCSI, etc.

Volume management treats PVs as sequences of chunks called physical extents (PEs). Volume managers may have PEs of a uniform size or of variable size PEs that can be split and merged.

Normally, PEs map one-to-one to logical extents (LEs). With mirroring of storage devices (multiple copies of data, e.g. on different storage devices), multiple PEs map to each LE. PEs are part of a physical volume group (PVG), a set of same-sized PVs that act similarly to hard disks in a RAID1 array. PVGs are usually stored on different disks and may also be on separate data buses to increase redundancy.

A system may pool LEs into a volume group (VG). The pooled LEs may then be joined or concatenated together in a logical volume (LV). An LV is a virtual partition. Systems may use an LV as a raw block device (also known as raw device, or block device) as though it was a physical partition. For example a storage system may create a mountable file system on an LV, or use an LV as swap storage, etc.

In this description, where the boundary and differences between a memory system and a storage system may be blurred, an LV may comprise one or more PMs and a PM may comprise one or more LVs. If there is the possibility of ambiguity or confusion, it may be noted when, for example, an LV comprises one or more PMs and when, for example, a PM may comprise one or more LVs.

FIG. 1A shows a multi-class memory apparatus 1A-100 for receiving instructions via a single memory bus, in accordance with one embodiment. As an option, the apparatus 1A-100 may be implemented in the context of any subsequent Figure(s). Of course, however, the apparatus 1A-100 may be implemented in the context of any desired environment.

As shown, a physical memory sub-system 1A-102 is provided. In the context of the present description, as set forth earlier, physical memory refers to any memory including physical objects or memory components. For example, in one embodiment, the physical memory may include semiconductor memory cells. Furthermore, in various embodiments, the physical memory may include, but is not limited to, flash memory (e.g. NOR flash, NAND flash, etc.), random access memory (e.g. RAM, SRAM, DRAM, MRAM, PRAM, etc.), a solid-state disk (SSD) or other disk, magnetic media, and/or any other physical memory that meets the above definition.

Additionally, in various embodiments, the physical memory sub-system 1A-102 may include a monolithic memory circuit, a semiconductor die, a chip, a packaged memory circuit, or any other type of tangible memory circuit. In one embodiment, the physical memory sub-system 1A-102 may take the form of a dynamic random access memory (DRAM) circuit. Such DRAM may take any form including, but not limited to, synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, etc.), graphics double data rate DRAM (GDDR, GDDR2, GDDR3, etc.), quad data rate DRAM (QDR DRAM), RAMBUS XDR DRAM (XDR DRAM), fast page mode DRAM (FPM DRAM), video DRAM (VDRAM), extended data out DRAM (EDO DRAM), burst EDO RAM (BEDO DRAM), multibank DRAM (MDRAM), synchronous graphics RAM (SGRAM), and/or any other DRAM or similar memory technology.

As shown, the physical memory sub-system 1A-102 includes a first memory 1A-104 of a first memory class and a second memory 1A-106 of a second memory class. In the context of the present description, as set forth earlier, a memory class may refer to any memory classification of a memory technology. For example, in various embodiments, the memory class may include, but is not limited to, a flash memory class, a RAM memory class, an SSD memory class, a magnetic media class, and/or any other class of memory in which a type of memory may be classified.

In the one embodiment, the first memory class may include non-volatile memory (e.g. FeRAM, MRAM, and PRAM, etc.), and the second memory class may include volatile memory (e.g. SRAM, DRAM, T-RAM, Z-RAM, and TTRAM, etc.). In another embodiment, one of the first memory 1A-104 or the second memory 1A-106 may include RAM (e.g. DRAM, SRAM, embedded RAM, etc.) and the other one of the first memory 1A-104 or the second memory 1A-106 may include NAND flash (or other nonvolatile memory, other memory, etc.). In another embodiment, one of the first memory 1A-104 or the second memory 1A-106 may include RAM (e.g. DRAM, SRAM, etc.) and the other one of the first memory 1A-104 or the second memory 1A-106 may include NOR flash (or other nonvolatile memory, other memory, etc.). Of course, in various embodiments, any number (e.g. 2, 3, 4, 5, 6, 7, 8, 9, or more, etc.) of combinations of memory classes may be utilized.

The second memory 1A-106 is communicatively coupled to the first memory 1A-104. In the context of the present description, being communicatively coupled refers to being coupled in any way that functions to allow any type of signal (e.g. a data signal, a control signal, a bus, a group of signals, other electric signal, etc.) to be communicated between the communicatively coupled items. In one embodiment, the second memory 1A-106 may be communicatively coupled to the first memory 1A-104 via direct contact (e.g. a direct connection, link, etc.) between the two memories. Of course, being communicatively coupled may also refer to indirect connections, connections with intermediate connections therebetween, etc. In another embodiment, the second memory 1A-106 may be communicatively coupled to the first memory 1A-104 via a bus. In yet another embodiment, the second memory 1A-106 may be communicatively coupled to the first memory 1A-104 utilizing a through-silicon via (TSV).

As another option, the communicative coupling may include a connection via a buffer device (logic chip, buffer chip, FPGA, programmable device, ASIC, etc.). In one embodiment, the buffer device may be part of the physical memory sub-system 1A-102. In another embodiment, the buffer device may be separate from the physical memory sub-system 1A-102.

In one embodiment, the first memory 1A-104 and the second memory 1A-106 may be physically separate memories that are communicatively coupled utilizing through-silicon via technology. In another embodiment, the first memory 1A-104 and the second memory 1A-106 may be physically separate memories that are communicatively coupled utilizing wire bonds. Of course, any type of coupling (e.g. electrical, optical, etc.) may be implemented that functions to allow the second memory 1A-106 to communicate with the first memory 1A-104.

The apparatus 1A-100 is configured such that the first memory 1A-104 and the second memory 1A-106 are capable of receiving instructions via a single memory bus 1A-108. The memory bus 1A-108 may include any type of memory bus. Additionally, the memory bus may be associated with a variety of protocols (e.g. memory protocols such as JEDEC DDR2, JEDEC DDR3, JEDEC DDR4, SLDRAM, RDRAM, LPDRAM, LPDDR, etc; I/O protocols such as PCI, PCI-E, HyperTransport, InfiniBand, QPI, etc; networking protocols such as Ethernet, TCP/IP, iSCSI, etc; storage protocols such as NFS, SAMBA, SAS, SATA, FC, etc; and other protocols (e.g. wireless, optical, etc.); etc.).

In one embodiment, the physical memory sub-system 1A-102 may include a three-dimensional integrated circuit. In the context of the present description, a three-dimensional integrated circuit refers to any integrated circuit comprised of stacked wafers and/or dies (e.g. silicon wafers and/or dies, etc.), which are interconnected vertically (e.g. stacked, compounded, joined, integrated, etc.) and are capable of behaving as a single device.

For example, in one embodiment, the physical memory sub-system 1A-102 may include a three-dimensional integrated circuit that is a wafer-on-wafer device. In this case, a first wafer of the wafer-on-wafer device may include the first memory 1A-104 of the first memory class, and a second wafer of the wafer-on-wafer device may include the second memory 1A-106 of the second memory class.

In the context of the present description, a wafer-on-wafer device refers to any device including two or more semiconductor wafers (or die, dice, or any portion or portions of a wafer, etc.) that are communicatively coupled in a wafer-on-wafer configuration. In one embodiment, the wafer-on-wafer device may include a device that is constructed utilizing two or more semiconductor wafers, which are aligned, bonded, and possibly cut in to at least one three-dimensional integrated circuit. In this case, vertical connections (e.g. TSVs, etc.) may be built into the wafers before bonding, created in the stack after bonding, or built by other means, etc.

In another embodiment, the physical memory sub-system 1A-102 may include a three-dimensional integrated circuit that is a monolithic device. In the context of the present description, a monolithic device refers to any device that includes at least one layer built on a single semiconductor wafer, communicatively coupled, and in the form of a three-dimensional integrated circuit.

In another embodiment, the physical memory sub-system 1A-102 may include a three-dimensional integrated circuit that is a die-on-wafer device. In the context of the present description, a die-on-wafer device refers to any device including one or more dies positioned on a wafer. In one embodiment, the die-on-wafer device may be formed by dicing a first wafer into singular dies, then aligning and bonding the dies onto die sites of a second wafer.

In yet another embodiment, the physical memory sub-system 1A-102 may include a three-dimensional integrated circuit that is a die-on-die device. In the context of the present description, a die-on-die device refers to a device including two or more aligned dies in a die-on-die configuration. Additionally, in one embodiment, the physical memory sub-system 1A-102 may include a three-dimensional package. For example, the three-dimensional package may include a system in package (SiP) or chip stack MCM.

In operation, the apparatus 1A-100 may be configured such that the first memory 1A-104 and the second memory 1A-106 are capable of receiving instructions from a device 1A-110 via the single memory bus 1A-108. In one embodiment, the device 1A-110 may include one or more components from the following list (but not limited to the following list): a central processing unit (CPU); a memory controller, a chipset, a memory management unit (MMU); a virtual memory manager (VMM); a page table, a table lookaside buffer (TLB); one or more levels of cache (e.g. L1, L2, L3, etc.); a core unit; an uncore unit (e.g. logic outside or excluding one or more cores, etc.); etc.). In this case, the apparatus 1A-100 may be configured such that the first memory 1A-104 and the second memory 1A-106 are be capable of receiving instructions from the CPU via the single memory bus 1A-108.

More illustrative information will now be set forth regarding various optional architectures and features with which the foregoing techniques discussed in the context of any of the figure(s) may or may not be implemented, per the desires of the user. For instance, various optional examples and/or options associated with the configuration/operation of the physical memory sub-system 1A-102, the configuration/operation of the first and second memories 1A-104 and 1A-106, the configuration/operation of the memory bus 1A-108, and/or other optional features have been and will be set forth in the context of a variety of possible embodiments. It should be strongly noted that such information is set forth for illustrative purposes and should not be construed as limiting in any manner. Any of such features may be optionally incorporated with or without the inclusion of other features described.

FIG. 1B

FIG. 1B shows an exemplary system using main memory with multiple memory classes, in accordance with another embodiment. As an option, the exemplary system of FIG. 1B may be implemented in the context of the architecture and environment of FIG. 1A, or any subsequent Figure(s). Of course, however, the exemplary system of FIG. 1B may be implemented in the context of any desired environment.

In FIG. 1B, System 1B-100 comprises a CPU 1B-102 connected (e.g. coupled, etc.) to Memory 1B-106 using a single Memory Bus 1B-104, and connected (e.g. coupled, etc.) to Chipset 1B-120 using I/O Bus #1 1B-116. In FIG. 1B Chipset 1B-120 is coupled to Disk 1B-110 using I/O Bus #2 1B-108. In FIG. 1B, Memory 1B-106 comprises memory class 1 1B-112 and memory class 2 1B-114. In FIG. 1B, Memory 1B-106 may also be the main memory for System 1B-100. In FIG. 1B, memory class 1 1B-112 and memory class 2 1B-114 may comprise different memory technologies. In FIG. 1B, Disk 1B-110 may be secondary storage for System 1B-100.

In various different embodiments, with reference to FIG. 1B and other figures referenced below and other embodiments described below, different system components (e.g. system blocks, chips, packages, etc.) may be constructed (e.g. physically, logically, arranged, etc.) in different ways; the coupling (e.g. logical and/or physical connection via buses, signals, wires, etc.) may be arranged in different ways; and the architectures may be arranged in different ways (e.g. operations performed in different ways, different split (e.g. partitioning, sectioning, assignment, etc.) of functions between hardware and/or software and/or firmware, etc.); but these various differences may not affect the basic descriptions (e.g. functions, operations, theory of operations, advantages, etc.) provided below for each embodiment.

Where appropriate for each embodiment, examples of alternative implementations, options, variations, etc. may be described, for example, where new concepts, elements, etc. may be introduced in an embodiment. However, these alternative implementations are not necessarily repeated for each and every embodiment though application of alternative implementations may be equally possible to multiple embodiments. For example, it may be initially explained that a memory component may be constructed from a package that may contain one die or one or more stacked die. These alternative memory component implementations may not be repeatedly explained for each and every embodiment that uses memory components. Therefore, the description of each embodiment described here may optionally be viewed as cumulative with respect to the various implementation options, alternatives, other variations, etc. in that each new or different etc. alternative implementation that may be applied to other embodiments should be viewed as having being described as such.

For example, in various embodiments, memory class 1 and memory class 2 may each be physically constructed (e.g. assembled, constructed, processed, manufactured, packaged, etc.) in several ways: from one or more memory components; from multi-chip packages; from stacked memory devices; etc. In various embodiments, memory class 1 and memory class 2 may be: integrated on the same die(s); packaged separately or together in single die package(s) or multi-chip package(s); stacked separately or together in multi-chip packages; stacked separately or together in multi-chip packages with one or more other chip(s); as discrete memory components; etc.

In different embodiments, Memory 1B-106 may be physically constructed (e.g. assembled, manufactured, packaged, etc.) in many different ways: as DIMM(s); as component(s); on a motherboard or other PCB; as part of the CPU or other system component(s); etc.

In one embodiment, Memory 1B-106 may comprise more than two memory classes, which may also be physically constructed in the various ways just described.

In one embodiment, there may be more than one CPU 1B-102. Additionally, in one embodiment, there may or may not be a Disk 1B-110. In another embodiment, CPU 1B-102 may be connected directly to Disk 1B-110 (e.g. there may or may not be a separate Chipset 1B-120, the function of Chipset 1B-120 may be integrated with the CPU 1B-102, etc.). In yet another embodiment, one or more CPU(s) may connect (e.g. couple, etc.) to more than one Memory 1B-106.

In various embodiments, Memory Bus 1B-104 may be: a standard memory bus (e.g. DDR3, DDR4 etc.); other standard bus (e.g. QPI, ARM, ONFi, etc.); a proprietary bus (e.g. ARM, packet switched, parallel, multidrop, point-to-point, serial, etc.); or even an I/O bus used for memory (e.g. PCI-E, any variant of PCI-E, Light Peak, etc.).

Additionally, in different embodiments, I/O Bus #1 1B-116 that couples CPU 1B-102 to Chipset 1B-120 may be: a standard I/O bus (e.g. PCI, PCI-E, ARM, Light Peak, USB, etc.); a proprietary bus (e.g. ARM, packet switched, parallel, multidrop, point-to-point, serial, etc.); or even a memory bus used, modified, altered, re-purposed etc. for I/O (e.g. I/O, chipset coupling, North Bridge to South Bridge coupling, etc.) purposes (e.g. low-power DDR, etc.). Of course, Chipset 1B-120 [or the functions (protocol conversion, etc.) of Chipset 1B-120] may be integrated with (e.g. combined with, part of, performed by, etc.) CPU 1B-102 etc.

Further, in various embodiments, I/O Bus #2 1B-108 that couples Chipset 1B-120 with Disk 1B-110 may be: a standard I/O or storage bus (e.g. SATA, SAS, PCI, PCI-E, ARM, Light Peak, USB, InfiniBand, etc.); a bus used to interface directly with solid-state storage (e.g. NAND flash, SSD, etc.) such as ONFi 1.0, ONFi 2.0, ONFi 3.0, OneNAND, etc; a proprietary bus (e.g. ARM, packet switched, parallel, multidrop, point-to-point, serial, etc.); a modified bus and/or bus protocol (e.g. lightweight version of a storage protocol bus for use with NAND flash, etc.); a networking bus and/or networking protocol (e.g. Ethernet, Internet, LAN, WAN, TCP/IP, iSCSI, FCoE, etc.); a networked storage protocol (e.g. NAS, SAN, SAMBA, CIFS, etc.); a wireless connection or coupling (e.g. 802.11, Bluetooth, ZigBee, LTE, etc.); a connection or coupling to offline storage (e.g. cloud storage, Amazon EC3, Mozy, etc.); a combination of buses and protocols (e.g. PCI-E over Ethernet, etc.); or even a memory bus used, modified, altered, re-purposed etc. for I/O purposes (e.g. low-power DDR, DDR2, etc.).

In different embodiments, for systems similar to, based on, or using that shown in FIG. 1B, any of the buses, protocols, standards etc. operable for I/O Bus #2 1B-108 may be used for I/O Bus #1 1B-116; and any of the buses, protocols, standards etc. operable for I/O Bus #1 1B-116 may be used for I/O Bus #2 1B-108.

Further, in various embodiments, Memory Bus 1B-104 and/or I/O Bus #1 1B-116 and/or I/O Bus #2 1B-108 may comprise: one or more buses connected in serial, one or more buses connected in parallel, one or more buses connected in combinations of serial and/or parallel; one or more buses in series or parallel plus control signals; one or more different buses in series plus control signals; and many other series/parallel data/address/control/ etc. bus combinations with various series/parallel control signal combinations, etc.

In different embodiments, Memory Bus 1B-104 and/or I/O Bus #1 1B-116 and/or I/O Bus #2 1B-108 may comprise: one or more buses using different protocols; different bus standards; different proprietary bus and/or protocol formats; combinations of these, etc.

In different embodiments, Memory Bus 1B-104 and/or I/O Bus #1 1B-116 and/or I/O Bus #2 1B-108 may comprise: a point to point bus; a multidrop bus; a parallel bus; a serial bus; a split transaction bus; one or more high-speed serial links; combinations of these; etc.

For example, in one embodiment, Memory Bus 104 may be a standard JEDEC (e.g. DDR2, DDR3, DDR4 etc.) memory bus that comprises a parallel combination of: a data bus [e.g. 64-bits of data, 72-bits (e.g. data plus ECC, etc.), etc.], an address bus, and control signals.

In another embodiment, Memory Bus 1B-104 may be a standard JEDEC (e.g. DDR2, DDR3, DDR4 etc.) memory bus or other memory bus that comprises a parallel combination of: a data bus [e.g. 64-bits of data, 72-bits (e.g. data plus ECC, etc.), etc.], an address bus, and non-standard control signals (e.g. either in addition to and/or instead of standard control signals, etc.). In one embodiment, control signals may time-multiplexed with existing standard control signals. In another embodiment, control signals may re-use existing control signals, or may re-purpose existing control signals, etc. Of course, in various embodiments, control signals may also be viewed as data, address, etc. signals. Equally, in one embodiment, address, data, etc. signals that may be part of a bus may also be used as control signals etc. In addition, in one embodiment, data signals may be used for control signals or address signals etc. For example, in some embodiments, a Bank Address signal (or signals) in a DDR protocol may be viewed and/or used as a control signal as well as an address signal. In other embodiments, one or more Chip Select signals in a DDR protocol may be used as one or more control signals and adapted to be used as one or more address signals, etc.

In another embodiment, I/O Bus #2 1B-108 may comprise a wireless connection to offline storage via a combination (e.g. series, series/parallel, parallel, combination of series and parallel, etc.) of different: buses (e.g. I/O bus, storage bus, etc); protocols (e.g. SATA, 802.11, etc.), adapters (wireless controllers, storage controllers, network interface cards, etc.); and different standards; and combinations of these, etc. For example, in some embodiments I/O Bus #2 1B-108 may be a wireless 802.11 connection that may be coupled to (e.g. chained with, in series with, connected to, etc.) a cell phone connection that is in turn coupled (e.g. in series with, coupled to, etc.) an Ethernet WAN connection etc. Of course, in various embodiments, these connections may be in any order or of any type.

In different embodiments, two or more of Memory Bus 1B-104 and/or I/O Bus #1 1B-116 and/or I/O Bus #2 1B-108 may share [e.g. through time-multiplexing, through switching, through multiplexing (e.g. other than time, etc.), through packet switching, etc.] some or all of the same connections (e.g. wires, signals, control signals, data buses, address buses, unidirectional signals, bidirectional signals, PCB traces, package pins, socket pins, bus traces, connections, logical connections, physical connections, electrical connections, optical connections, etc.).

In different embodiments, one or more of the bus(es) that comprise Memory Bus 104 and/or I/O Bus #1 1B-116 and/or I/O Bus #2 1B-108 may be wireless (e.g. LTE, 802.11, Wi-Max, etc.). Thus, for example, in a system that includes a mobile phone (e.g. a cellular phone, etc.), the mobile phone may have some memory (e.g. solid-state memory, disk storage, etc.) located remotely using a wireless connection (in which case one system may be viewed as being the cell phone, and another system as being the cell phone plus remote storage).

In different embodiments, one or more of the bus(es) that comprise Memory Bus 1B-104 and/or I/O Bus #1 1B-116 and/or I/O Bus #2 1B-108 may be optical (e.g. Fibre Channel, Light Peak, use optical components, etc.). Thus, for example, in a system that comprises a server with a requirement for large amounts of high-speed memory and having a large power budget etc, the CPU may have memory connected via optical cable (e.g. optical fiber, fibre channel, optical coupling, etc.).

Of course, any technique of coupling (e.g. connecting logically and/or physically, using networks, using switches, using MUX and deMUX functions, encoding multiple functions on one bus, etc.) may be used for any (or all) of the buses and to connect any (or all) of the components that may be coupled.

In different embodiments, the multiple memory classes in Memory 1B-106 and Memory Bus 1B-104 may be connected (e.g. coupled, etc.) to each other in several different ways depending on the architecture of Memory 1B-106. Various embodiments of the architecture of Memory 1B-106 and the rest of the system are described in detail in exemplary embodiments that follow. It should be noted now, however, that in order to allow Memory 1B-106 to contain multiple memory classes and connect (e.g. couple, etc.) to CPU 1B-102, other components (e.g. chips, passive components, active components, etc.) may be part of Memory 1B-106 (or otherwise connected (e.g. coupled, joined, integrated etc.) with the multiple memory classes). Some other components, their functions, and their interconnection(s), which, in various embodiments, may be part of Memory 1B-106, are described in detail below. It should be noted that these other components, their functions, and their interconnection(s), which may be part of Memory 1B-106, may not necessarily be included or be shown in all figures.

FIG. 1C

FIG. 1C shows a virtual memory (VMy) in an example of a computer system using a main memory with multiple memory classes, in accordance with another embodiment. As an option, the exemplary system of FIG. 1C may be implemented in the context of the architecture and environment of the previous Figure(s), or any subsequent Figure(s). Of course, however, the exemplary system of FIG. 1C may be implemented in the context of any desired environment.

A VMy may contain pages that may be either located (e.g. resident, stored, etc) in main memory or in a page file (also called a swap file). In FIG. 1C, a System 120 includes a CPU 122 coupled to Memory 126 using Memory Bus 124, and coupled to Disk 130 using I/O Bus 128. The system of FIG. 1C is similar to FIG. 1B except that the Disk 130 is coupled directly to CPU 122 in FIG. 1C.

In some high-end CPUs the function of chipset, South Bridge, disk controller, etc. may be integrated, but in some low-end systems (and consumer devices, for example), it may not be integrated. It should be noted that in any of the embodiments shown or described herein a chipset, South Bridge, disk controller, I/O controller, SATA controller, ONFi controller, PCI-E controller, etc. may or may not be connected to the CPU and/or may or may not be integrated with the CPU.

In FIG. 1C, memory class 1 148, memory class 2 150 and memory class 3 134 located on Disk 130 may together form VMy 132. In FIG. 1C, memory class 1 148 and memory class 2 150 may form the Main Memory 138. In FIG. 1C, memory class 3 134 located on Disk 130 may contain the Page File. In FIG. 1C, memory class 3 134 is not part of main memory (but in other embodiments it may be). In FIG. 1C, the Data 136 of Disk 130 may be used for data storage and is not part of VMy 132 (but in other embodiments it may be).

In one embodiment, memory class 1 148, memory class 2 150 and memory class 3 134 may be composed of (e.g. logically comprise, etc.) multiple different classes of PM (e.g. selected from: SRAM, SDRAM, NAND flash, embedded DRAM, PCRAM, MRAM, combinations of these and/or other memory types, etc.).

In FIG. 1B, all of Memory 106, which included multiple memory classes, may be main memory for System 100. In FIG. 1C regions of memory are labeled as memory, main memory, and virtual memory. In FIG. 1C, the regions labeled memory and main memory are the same; but this is not always so in other embodiments and thus may stretch the precision of the current terminology. Therefore, in FIG. 1C, system components are labeled using a taxonomy that will help explain embodiments that contain novel aspects for which current terminology may be inadequate. In this case, elements of CPU cache terminology are borrowed. Thus, in FIG. 1C, the CPU Core 140 is shown as coupled to L1 Cache 142 and (indirectly, hierarchically) to L2 Cache 144. The L1 Cache and L2 Cache form a hierarchical cache with L1 Cache being logically closest to the CPU. Using a similar style of labeling in FIG. 1C for the VMy components, memory class 1 148 is labeled as M1 Memory, memory class 2 150 as M2 Memory and memory class 3 134 as M3 Memory (M1, M2, M3 may generally be used, but it should be understood that this is a short abbreviation, L1 Cache as just will be referred to L1). M1 may also be referred to as primary memory, M2 as secondary memory, M3 as tertiary memory, etc.

The logical labels for CPU cache, L1 and L2 etc, say nothing about the physical technology (e.g. DRAM, embedded DRAM, SRAM, etc.) used to implement each CPU cache. In the context of the present description, there is a need to distinguish between memory technologies used for VMy components M1, M2 etc. because the technology used affects such things as system architecture, buses, protocols, packaging, etc. Thus, following a similar style of labeling to the VMy components in FIG. 1C, memory class 1 is labeled as C1, memory class 2 as C2, and memory class 3 as C3. Note that number assigned to memory class and the number assigned to the logical position of the class are not necessarily the same. Thus, both M1 and M2 may be built from memory class 1 (e.g. where memory class 1 might be SDRAM, etc.). For example, a component of memory may be referred to as M2.C1, which refers to M2 composed of memory class 1.

In FIG. 1C buses are also labeled as B1 (for Memory Bus) and B2 (for I/O Bus). Memory bus technologies and I/O bus technologies are deliberately not distinguished because the embodiments described herein may blur, merge, and combine, etc. those bus technologies (and to a great extent various embodiments remove the distinctions between I/O bus technologies and memory bus technologies). The concept of hierarchy in bus technologies may be maintained. Thus, when it is convenient, B1 and B2 may be used to point out that B1 may be closer to the CPU than B2. It should be noted that in many situations (e.g. architectures, implementations, embodiments, etc.) it is sometimes hard to define what closer to the CPU means with a bus technology. Nevertheless in FIG. 1C for example B1 is regarded as being closer (e.g. lower latency in this case) to the CPU than bus B1. Thus, B1 may be referred to as the primary bus, B2 as the secondary bus, etc. The Page File in FIG. 1C may be referred to as being memory B2.M3.C3, e.g. tertiary memory M3 is constructed of memory class 3 technology and is located on secondary bus B2.

In general, though not necessarily always, M1 may be logically closest to the CPU, M2 next, and so on. If there is a situation in which, for example, M1 and M2 are not in that logical position and there is possible confusion, this may be pointed out. It may not be obvious why the distinction between M1 and M2 might not be clear, thus, some embodiments may be described where the distinction between M1 and M2 (or M2 and M3, M1 and M3, etc.) is not always clear.

In one embodiment, for example, memory may be composed of M1 and M2 with two different technologies (e.g. C1 and C2), but both connected to the same bus (e.g. at the same logical distance from the CPU); in that case it may be the case that both technologies are M1 (and thus there may be M1. C1 and M1.C2 for example) or it may be the case that if one technology has lower latency, for example C1, than that faster technology is M1 because it is closer to the CPU in the sense of lower latency and thus there is M1.C1 (with the other, slower technology C2, being M2 and thus M2.C2).

In another embodiment, a technology C1 used for M1 may be capable of operating in different modes and is used in a memory system together with technology C2 used as M2. Suppose, for example, mode 1 of C1 is faster than C2, but mode 2 of C1 is slower than M2. In that case, the roles of C1 and C2 used as M1 and M2, for example, may be reversed in different modes of operation of C1. In this case, where the fastest memory is defined as being closer to the CPU, terminology may be used to express that memory is composed of M1.C1 and M2.C2 when C1 is in mode 1 and memory is composed of M1.C2 and M2.C1 when C1 is in mode 2.

In FIG. 1C, that portion of Disk 130 and Secondary Storage 146 that is used for Data 136 as labeled as D1. This notation may be helpful in certain embodiments where the distinction between, for example, page file regions of a disk (or memory) and data regions of a disk (or memory) needs to be clear. Although not labeled in FIG. 3, if the data region uses memory class 3 (disk technology in FIG. 1C), the data region of the disk may be labeled as B2.C3.D1 in FIG. 1C for example (and the page file, labeled memory class 3 134 in FIG. 1C may be more accurately referred to as B2.C3.M3).

In some embodiments, different memory technologies (e.g. solid-state, RAM, DRAM, SDRAM, SRAM, NAND flash, MRAM, etc.) as well as storage technologies (e.g. disk, SSD, etc.) all have individual and different physical, logical, electrical and other characteristics, and thus each technology may, for example, have its own interface signaling scheme, protocol, etc. For example, DRAM memory systems may use extremely fast (e.g. 1 GHz clock frequency or higher, etc.) and reliable (e.g. ECC protected, parity protected, etc.) memory bus protocols that may be industry standards: e.g. JEDEC standard DDR2, DDR3, DDR4, protocols etc. Disks (e.g. mechanical, SSD, etc.) may use fast, reliable and easily expandable storage device protocols that may be industry standards: e.g. ANSI/INCITS T10, T11 and T13 standards such as SCSI, SATA, SAS protocols, etc. and may be attached (e.g. coupled, connected, etc. via a controller, storage controller, adapter, host-bus adapter, HBA etc.) to I/O bus protocols that may also be industry standards: e.g. PCI-SIG standards such as PCI-Express, PCI, etc.

The following definitions and the following explanation of the operation of a VMy are useful in the detailed description of different and various embodiments of the memory system below.

To create the illusion of a large memory using a small number of expensive memory components together with other cheaper disk components a system may employ VMy. The information (e.g. data, code, etc.) stored in memory is a memory image. The system (e.g. OS, CPU, combination of the OS and CPU, etc.) may divide (e.g. partition, split, etc.) a memory image into pages (or virtual pages), and a page of a memory image can at any moment in time exist in (fast but expensive) main memory or on (slower but much cheaper) secondary storage (e.g. disk, SSD, NAND flash, etc.), or both (e.g. main memory and secondary storage). A page may be a continuous region of VMy in length (a standard length or size is 4,096 byte, 4 kB, the page size). A page may be page-aligned, that is the region (e.g. portion, etc.) of a page starts at a virtual address (VA) evenly (e.g. completely, exactly, etc.) divisible by the page size. Thus, for example, a 32-bit VA may be divided into a 20-bit page number and a 12-bit page offset (or just offset).

System 120 may contain an operating system (OS). For an OS that uses VMy, every process may work with a memory image that may appear to use large and contiguous sections of PM. The VMy may actually be divided between different parts of PM, or may be stored as one or more pages on a secondary storage device (e.g. a disk). When a process requests access to a memory image, the OS may map (or translate) the VA provided by the process to the physical address (PA, or real address). The OS may store the map of VA to PA in a page table.

A memory management unit (MMU) in the CPU may manage memory and may contain a cache of recently used VA to PA maps from the page table. This cache may be the translation lookaside buffer (TLB). When a VA in VMy needs to be translated to a PA, the TLB may be searched (a TLB lookup) for the VA. If the VA is found (a TLB hit), the corresponding PA may be returned and memory access may continue. If the VA is not found (a TLB miss), a handler may look up the address map in the page table to see whether the map exists by performing page table lookup or page walk. If the map exists in the page table, the map may be written to the TLB. The instruction that caused the TLB miss may then be restarted. The subsequent VA to PA translation may result in a TLB hit, and the memory access may continue.

A page table lookup may fail (a page miss) for two reasons. The first reason for a page miss is if there is no map available for the VA, and the memory access to that VA may thus be invalid (e.g. illegal, erroneous, etc.). An invalid access should be a rare event and may occur because of a programming error etc, and the operating system may then send a segmentation fault to the process, and this may be a fatal event. The second and normal reason for a page miss is if the requested page is not resident (e.g. present, stored, etc.) in PM. Such a page miss may happen when the requested page (e.g. page 1) has been moved out of PM and written to the page file, e.g. disk, normally in order to make room for another page (e.g. page 2). The usual term for this process is swapping (hence the term swap file) and it may be said that the pages (e.g. page 1 and page 2) have been swapped. When this page miss happens the requested page needs to be read (often referred to as fetched) from the page file on disk and written back into PM. This action is referred to a page being swapped out (from main memory to disk and the page file) and/or swapped in (from the disk and page file to main memory).

There are two situations to consider on a page miss: the PM is not full and PM full. When the PM is not full, the requested page may be fetched from the page file, written back into PM, the page table and TLB may be updated, and the instruction may be restarted. When the PM is full, one or more pages in the PM may be swapped out to make room for the requested page. A page replacement algorithm may then choose the page(s) to swap out (or evict) to the page file. These evicted page(s) may then be written to the page file. The page table may then be updated to mark the evicted page(s) that were previously in PM as now in the page file. The requested page may then be fetched from the page file and written to the PM. The page table and TLB may then be updated to mark the requested page that was in the page file as now in the PM. The TLB may then be updated by removing reference(s) to the evicted page(s). The instruction may then be restarted.

FIG. 2

FIG. 2 shows a page write in a system using main memory with multiple memory classes, in accordance with another embodiment. As an option, the exemplary system of FIG. 2 may be implemented in the context of the architecture and environment of the previous Figure(s), or any subsequent Figure(s). Of course, however, the exemplary system of FIG. 2 may be implemented in the context of any desired environment.

In FIG. 2, a System 200 includes a CPU 202 coupled to Memory 226 using Memory Bus 204, and coupled to Disk 210 using I/O Bus 212. In FIG. 2, memory class 1 206 (M1), memory class 2 208 (M2) and memory class 3 234 (M3) located on Disk 210 together form VMy 232. In FIG. 2, memory class 1 206 and memory class 2 208 form the Main Memory 238. In FIG. 2, memory class 3 234 located on Disk 210 contains the page file. In FIG. 2, memory class 3 234 is not part of Main Memory 238 (but in other embodiments it may be).

In FIG. 2, a page of memory (for example Page X 214) is located in memory class 1 206, but is not immediately needed by the CPU 202. In some embodiments memory class 1 206 may be small and fast but expensive memory (e.g. SDRAM, SRAM, etc.). In this case, Page X may be fetched from memory class 1 206 and copied to a location on larger, slower but cheaper secondary storage (e.g. Page X 216). In order to complete the transfer of Page X from memory class 1 206 to Disk 210, the data comprising Page X may be copied (e.g. transferred, moved. etc.) as Copy 1 220 over Memory Bus 204, through CPU 202, through I/O Bus 212, to the location of Page X 216 on Disk 210. This process of Copy 1 220 may, in some embodiments, free up precious resources in memory class 1 206. However, one possible result is that the process of Copy 1 220 may consume time and may also consume various other resources including bandwidth (e.g. time, delay, etc.) on Memory Bus 204, bandwidth (e.g. time, delay, etc.) on I/O Bus 208, bandwidth (e.g. time, delay, etc.) and write latency (e.g. delay, cycles, etc.) of Disk 210, and possibly also resources (e.g. cycles, etc.) from the CPU 202. In addition another possible result may be that power is consumed in all these operations.

In different embodiments, the Copy 1 220 may be part of a page swap, a page move, a write to disk, etc. If Copy 1 220 is part of a page swap then the next operation may be to copy Page Y 236 to memory class 1 206 in order to replace Page X 214.

In some embodiments, the system designer may accept the trade-offs just described and design a system having the memory architecture shown in FIG. 2. In other embodiments that are described below, some of these trade-offs just described may be changed, improved or otherwise altered etc. by changing the architecture of the memory system.

In other embodiments, based on that shown in FIG. 2 and/or based on other similar embodiments described elsewhere, Disk 210 may be: remote storage using e.g. SAN; NAS; using a network such as Ethernet etc. and a protocol such as iSCSI, FCoE, SAMBA, CIFS, PCI-E over Ethernet, InfiniBand, USB over Ethernet, etc; cloud storage using wired or wireless connection(s); RAID storage; JBOD; SSD; combinations of these, etc. and where the storage may be disk(s), SSD, NAND flash, SDRAM, RAID system(s), combinations of these, etc.

FIG. 3

FIG. 3 shows a page read in a system using main memory with multiple memory classes, in accordance with another embodiment. As an option, the exemplary system of FIG. 3 may be implemented in the context of the architecture and environment of the previous Figure(s), or any subsequent Figure(s). Of course, however, the exemplary system of FIG. 3 may be implemented in the context of any desired environment.

In FIG. 3, a System 300 includes a CPU 302 coupled to Memory 326 using Memory Bus 304, and coupled to Disk 310 using I/O Bus 312. In FIG. 3, memory class 1 306 (M1), memory class 2 308 (M2) and memory class 3 334 (M3) located on Disk 310 together form VMy 332. In FIG. 3, memory class 1 306 and memory class 2 306 form the Main Memory 338. In FIG. 3, memory class 3 334 located on Disk 310 contains the page file. In FIG. 3, memory class 3 334 is not part of Main Memory 338 (but in other embodiments it may be).

In FIG. 3, a page of memory (e.g. Page Y 318, etc.) is located on Disk 310, but is immediately needed by the CPU 302, In some embodiments, memory class 1 306 may be small and fast but expensive memory (e.g. SDRAM, SRAM, etc.). In this case, Page Y located on larger, slower but cheaper secondary storage (e.g. Page Y 336) may be fetched from and copied to a location in memory class 1 306. In order to complete the transfer of Page Y from Disk 310 to memory class 1 306, the data comprising Page Y is copied (e.g. transferred, moved. etc.) as Copy 2 320 through I/O Bus 212, through CPU 302, over Memory Bus 304, to the location of Page X 318 to memory class 1 306. This process of Copy 2 320 may, in some embodiments, allow for providing CPU 302 faster access to Page Y. However, the process of Copy 2 320 may, in some embodiments, allow for consuming time and may also consume various other resources including bandwidth (e.g. time, delay, etc.) on Memory Bus 304, bandwidth (e.g. time, delay, etc.) on I/O Bus 308, bandwidth (e.g. time, delay, etc.) and write latency (e.g. delay, cycles, etc.) of Disk 310, and possibly also resources (e.g. cycles, etc.) from the CPU 302. In addition, power is consumed in all these operations.

The operations in the systems of FIG. 2 and FIG. 3 are described separately above, but it should be noted that that if the operations (e.g. steps, actions, etc.) shown in FIG. 2 are performed (e.g. Copy 1 220, copying Page X from main memory to the swap file, etc.) followed by the operations shown in FIG. 3 (e.g. Copy 2 320, copying Page Y from the swap file to main memory, etc.) in a system Page X (shown as Page X 316 in FIG. 3) and Page Y are swapped in main memory; with the final result being as shown in FIG. 3. These page swapping operations are a sequence of operations that may be performed via a virtual memory manager (VMM) or in virtual memory management. The time, power and efficiency of these VMM operations, including page swapping, are an element of system design and architecture.

In some embodiments, memory class 1 206 in FIG. 2 and memory class 1 306 in FIG. 3 may be small and fast but expensive memory (e.g. SDRAM, SRAM, etc.) as described above. In certain embodiments, memory class 1 206 in FIG. 2 and memory class 1 306 in FIG. 3 may be faster than memory class 2 208 in FIG. 2 and memory class 2 308 in FIG. 3. In these embodiments, the page eviction and page fetch are from (for eviction) and to (for fetch) the faster part of main memory.

In other embodiments, it may be desirous (e.g. for reasons of cost, power, performance, etc.) for memory class 1 206 in FIG. 2 and memory class 1 306 in FIG. 3 to be slower than memory class 2 208 in FIG. 2 and memory class 2 308 in FIG. 3. In these embodiments the page eviction and page fetch are from and to the slower part of main memory.

Of course, there may be possible trade-offs in the design of systems similar to those shown in FIG. 2 and FIG. 3 (e.g. portable consumer devices, servers, laptops, cell phones, tablet PCs, etc.). For example, in some embodiments, it may be desirous to perform swapping to and from a memory class that has one or more of the following properties relative to other memory classes in main memory: consumes less power (e.g. LPDDR rather than DDR, low-voltage memory, etc.); is more reliable (e.g. uses ECC protection, LDPC protection, parity protection, etc.); is removable (e.g. USB key, ReadyBoost, etc.); can be remotely connected more easily (e.g. SAN, NAS, etc.); is more compact (e.g. embedded DRAM rather than SRAM, flash rather than SRAM, etc.); is cheaper (e.g. flash rather than SDRAM, disk rather than SDRAM, etc.); can be more easily integrated with other component(s) (e.g. uses the same protocol, uses compatible process technology, etc.); has a more suitable protocol (e.g. ONFi, DDR, etc.); is easier to test (e.g. standard DDR SDRAM with built-in test (BIST, etc.), etc.); is faster (e.g. SRAM rather than flash, etc.); has higher bandwidth (e.g. DDR3 rather than DDR2, higher bus widths, etc.); can be stacked more easily (e.g. appropriate relative die sizes for stacking (for TSV stacking, wirebond, etc.), using TSVs with compatible process technologies, etc; can be packaged more easily (e.g. NAND flash with relatively low clock speeds may be wirebonded, etc.); can be cooled more easily (e.g. lower power NAND flash, low-power SDRAM, LPDDR, etc.); and/or any combinations of these; etc.

In other embodiments, the decision to swap pages to/from a certain memory class may be changed (e.g. by configuration; by the system, CPU, OS, etc; under program control; etc.). For example, a system may have main memory comprising memory class 1 and memory class 2 and suppose memory class 1 is faster than memory class 2, but memory class 1 consumes more power than memory class 2. In one embodiment, the system may have a maximum performance mode for which the system (e.g. CPU, OS, etc.) may use memory class 1 to swap to/from. The system may then have a maximum battery life mode in which the system may use memory class 2 to swap to/from.

In FIG. 2 the process of page eviction in a VMy system is described, but the process of page eviction may be similar to a data write from main memory to disk. In FIG. 3 the process of page fetch in a VMy system is described, but the process of page fetch may be similar to a data read from disk to main memory. Thus, the same issues, trade-offs, alternative embodiments, system architectures etc. that was described with regard to the systems in FIG. 2 and FIG. 3 (and systems similar to those systems) are relevant and may be used in systems that do not use a VMy architecture, but that may still benefit from the use of main memory with multiple memory classes. Thus, the descriptions and concepts may be broadened and therefore implement a variety of embodiments described to the physical memory sub-system general I/O and data movement rather than just the page operations involved in VMM. Of course, general I/O and data movement may involve copying, moving, shifting, replicating etc. different sizes of data other than a page.

In some embodiments, the system (e.g. OS, CPU, etc.) may track (e.g. with modified page table(s), etc.) which pages are located in which memory class in main memory. Descriptions of various embodiments that follow describe how the system (e.g. OS, CPU, etc.) may communicate (e.g. signal, command, send control information, receive status, etc.) with the memory to, for example, transfer (e.g. copy, move, DMA, etc.) data (e.g. pages, cache lines, blocks, contiguous or non-contiguous data structures, words, bytes, any portion of memory or storage, etc.) between multiple memory classes.

In other embodiments, the main memory system may autonomously (e.g. without knowledge of the CPU, OS etc.) decide which pages are located in which memory class in main memory. For example, data may be moved from one memory class to another due to constraints such as: power, performance, reliability (e.g. NAND flash wear-out, etc.), available memory space, etc. Such an embodiment may be opted for because (since the CPU and/or OS are oblivious that anything has changed) an implementation may require minimal changes to CPU and/or OS, etc. For example, suppose a system has main memory comprising memory class 1 and memory class 2. Suppose that a page (or any other form, portion, group, etc. of data; a page will be used for simplicity of explanation here and subsequently) is moved from memory class 1 to memory class 2. There may be a need for some way to hide this page move from the CPU. One reason that the use of a VMy system in FIG. 1B and the process of page swapping in FIG. 2 and FIG. 3 is described is that in some embodiments, the memory management systems (e.g. VMM in CPU, MMU in CPU, software in OS, combinations of these possibly with new hardware and/or software, etc.) may be used to allow the main memory to hide (either partially or completely from the CPU and/or OS) the fact that there are multiple memory classes present.

In some embodiments, the system designer may accept the trade-offs just described and design a system with (or similar to) the architecture shown in FIG. 2 and in FIG. 3, that may include some form of secondary storage for paging. In other embodiments, the slower speeds of disk I/O and secondary storage may lead to the functions of disk and secondary storage being moved to one or more of the memory classes in main memory. Such optional embodiments are described in more detail below.

In various embodiments, the page swap functions and memory reads/writes may still involve some form of secondary storage but be more complex than that described already. For example, page eviction (to make room for another page) may occur using a copy from one memory class in main memory (the eviction class) to another memory class (but still in main memory rather than secondary storage), possibly followed by a copy to secondary storage (e.g. disk, etc.). In another embodiment, page fetch may be a copy from secondary storage to one memory class in main memory (the fetch class, not necessarily the same as the eviction class) and then another copy to a second memory class in main memory.

In different embodiments, page files (or any other data, page files are used for simplicity of explanation) may exist just in secondary storage, just in main memory, in more than one memory class in main memory, or using combinations of these approaches (and such combinations may change in time). Copies of page files (or any other data, page files are used for simplicity of explanation) may be kept in various memory classes in main memory under configuration and/or system control, etc. Further and more detailed explanations of such optional embodiments are described below.

In different embodiments, the fetch class, the eviction class, the class (or classes) assigned to each of the fetch class and the eviction class may be changed in various ways: dynamically, at start up, at boot time, via configuration, etc.

Of course, as already discussed, a page fetch operation may be analogous to a disk (or other I/O) read; and a page eviction may be analogous to a disk (or other I/O) write; thus the preceding description of alternative architectures and logical structures for a system that does use VMy (with main memory using multiple memory classes) and page swapping applies equally to systems that do not use VMy but still perform disk (or other) I/O.

The systems in FIG. 2 and FIG. 3 have been described in terms of a VMy system, but the concept of swapping regions of the memory image in and out of main memory is a more general one. For example, machines without dedicated VMy support in the CPU may use overlays in order to expand main memory, in still other possible embodiments.

In general, using overlays (or overlaying) may involve replacement of a block (e.g. region, portion, page, etc.) of information stored in a memory image (e.g. instructions, code, data, etc.) with a different block. The term blocks is used for overlays to avoid confusion with pages for a VMy, but they may be viewed as similar [e.g. though page size(s) and block size(s), etc. may be different; there may be variable overlay block sizes; software and hardware used to manipulate pages and blocks may be different, etc.]. Overlaying blocks allows programs to be larger than the CPU main memory. Systems such as embedded systems, cell phones, etc. may use overlays because of the very limited size of PM (e.g. due to cost, space, etc.). Other factors that may make the use of overlays in systems such as those shown in FIG. 2 and FIG. 3 more attractive than VMy may include one or more of the following: the PM may be integrated (or packaged with, die stacked, etc.) a system-on-chip (e.g. SoC, CPU, FPGA, etc.) further limiting the PM size; any CPU if used may not have a VMy MMU; any OS if used may be a real-time OS (RTOS) and the swapping of overlay blocks may be more deterministic than page swapping in VMy; any OS used may not support VMy; etc. For the same reasons that one may opt for use of main memory with multiple memory classes for a VMy system, one may also opt to use main memory with multiple memory classes for an overlay system (or any other system that may require more main memory than PM available). Thus, even though the use of VMy may be described in a particular embodiment, any embodiment may equally use overlays or other techniques.

In some embodiments, one may opt to use overlays even if the system supports (e.g. is capable of using, uses, etc.) VMy. For example, in some systems using VMy, overlays may be used for some components (e.g. software, programs, code, data, database, bit files, other information, etc.) that may then be loaded as needed. For example, overlays may be kept in memory class 2 and swapped in and out of memory class 1 as needed.

Of the time-consuming (e.g. high delay, high latency, etc.) operations mentioned above, the most time-consuming (highest latency) operations may be those operations involving access to the disk(s) (e.g. with rotating magnetic media, etc.). Disk access times (in 2011) may be 10's of milliseconds (ms, 10^-3 seconds) or 10 million times slower compared to the access times for DRAM of a few nanoseconds (ns, 10^-9 seconds) or faster. Though caching may be employed in systems where faster access times are required there is a performance penalty for using disk (or other secondary storage separate from main memory, etc.) in a system with VMy, overlays, etc. Thus, in mobile consumer devices for example, one embodiment may eliminate the use of a disk (or other secondary storage separate from main memory, etc.) for paging, etc. A potential replacement technology for disk is NAND flash. A simple approach would be to replace the rotating disk used as secondary storage on the I/O bus with a faster SSD based on NAND flash technology. For reasons explained in the embodiments described below, one may opt to integrate technologies such as NAND flash (or other similar memory types, etc.) into main memory. The next several embodiments describe how the integration of different memory technologies into main memory may be achieved.

FIG. 4

FIG. 4 shows copy operations corresponding to memory reads in a system using main memory with multiple memory classes, in accordance with another embodiment. As an option, the exemplary system of FIG. 4 may be implemented in the context of the architecture and environment of the previous Figure(s), or any subsequent Figure(s). Of course, however, the exemplary system of FIG. 4 may be implemented in the context of any desired environment.

In explaining the copy operations corresponding to memory reads in the context of FIG. 4, optional features that may be achieved using multiple classes in main memory will be described. In FIG. 4, a System 400 includes a CPU 402 coupled to Memory 426 using Bus #1 404, coupled to Storage #1 410 using Bus #2 412, and coupled to Storage #2 430 using Bus #3 432. In FIG. 4 Storage #1 contains Data #1 442. In FIG. 4 Storage #2 430 contains Data #2 440. In FIG. 4, memory class 1 406, memory class 2 408, with memory class 3 434 and memory class 4 436 (both located on Storage #1 410) together form VMy 432. In FIG. 4, memory class 1 406 and memory class 2 408 form the Main Memory 438. In FIG. 4, memory class 3 434 forms a cache for Storage #1 410 and Disk #1 444. In FIG. 4, memory class 4 436 located on Storage #1 410 contains the page file. In FIG. 4, memory class 3 434 and memory class 4 436 are not part of Main Memory 438 (but in other embodiments they may be).

FIG. 4 is intended to be a representative example of a system while still showing various features that may be present in multiple embodiments. Thus, for example, not all systems may have Storage #2 430, but it has been included in the system architecture diagram of FIG. 4 to show, as just one example, that some systems may be coupled to a remote storage via a wireless connection (e.g. such that at least part of Bus #3 432 may be a wireless connection in some embodiments, etc.). As another example, Bus #2 412 (e.g. part, or all, etc.) may be a remote connection (e.g. wireless or other network, etc.) allowing paging to be performed to/from remote storage. As another example, not all systems may have memory class 3 434 that may act as a cache for Storage #1 410. As another example, Storage #1 410 may not be a rotating disk but may be a solid-state disk (SSD) and possibly integrated with one or more other solid-state memory components shown in FIG. 4 that may be part of Memory 426.

In FIG. 4, various alternative copy operations (Copy 3 453, Copy 4 454, Copy 5 455, Copy 6 456, Copy 7 457, Copy 8 458, Copy 9 459) have been diagrammed. These copy operations perform on various pages (Page 00 480, Page 01 481, Page 02 482, Page 03 483, Page 04 484, Page 05 485, Page 06 486).

It should be noted that the term copy should be broadly construed in that each copy may, in various embodiments, be: (a) a true copy (e.g. element 1 in location 1 before a copy operation and two elements after a copy operation: element 1 in location 1 and element 2 in location 2, with element 2 being an exact copy of element 1); (b) a move (e.g. element 1 in location 1 before the copy operation, and element 1 in location 2 after the copy operation); (c) copy or move using pointers or other indirection; (d) copy with re-location (element 1 in location 1 before the copy operation and two elements after the copy operation: element 1 in location 2 and element 2 in location 3, with element 2 being an exact copy of element 1, but locations 1, 2, and 3 being different); (e) combinations of these and/or other move and/or copy operations, etc.

In some embodiments, a copy of types (a)-(e) may result, for example, from software (or other algorithm, etc.) involved that may not be described in each and every embodiment and that, in general, may or may not be implemented in any particular embodiment.

The copy operations shown in FIG. 4 will be now described.

Copy 3 453 shows a copy from memory class 1 to memory class 3. This copy may be part of a page eviction or a write, for example. Copy 3 uses Bus #1 and Bus #2 as well as CPU resources. The lines of Copy 3 in FIG. 4 have been drawn as straight lines next to (parallel with) the bus(es) that is/are being used during the copy, but the lines have not necessarily been drawn representing the other copies in a similar fashion.

Copy 4 454 may follow Copy 3. For example, suppose that memory class 3 may act as a cache for Storage #1 410 then Copy 4 shows a next action following Copy 3. In the case of Copy 4 the write completes to memory class 4. Supposing that memory class 4 436 located on Storage #1 410 contains the page file then Copy 3 and Copy 4 together represent a page eviction.

Copy 5 455 may be an alternative to Copy 3. For various reasons, one may opt to perform Copy 5 instead of Copy 3. For example, Copy 3 may take longer than the time currently available; Copy 3 may consume CPU resources that are not currently available; Copy 3 may require too much power at the present time, etc. Copy 5 copies from memory class 1 to memory class 2 within Main Memory 438. For example, in the case of page eviction, a page is evicted to memory class 2 instead of to the page file on Storage #1 410. In some embodiments, two page files may be maintained, one on Storage #1 410 and one in memory class 2 (for example memory class 2 may contain more frequently used pages, etc.). In other embodiments, Copy 5 may be treated as a temporary page eviction and complete the page eviction (or data write in the case of a data write) to Storage #1 410 at a later time. Note that, in contrast to Copy 3, and depending on how the Main Memory is constructed, Copy 5 may not require Bus #1 or CPU resources (or may at least greatly decrease demands on these resources) and alternative embodiments and architectures will be described for Main Memory that have such resource-saving features below. These features may accompany using main memory with multiple memory classes. In different embodiments, the page eviction (or data write) may be completed in different ways, two examples of which are described next.

Copy 6 456 shows the first part of the case (e.g. represents an action performed) in which, for example, a temporary page eviction is reversed (or page eviction completed, etc.). Suppose, for example, that Copy 5 has been performed (and Copy 5 is treated as a temporary eviction) and following Copy 5 (possibly after a controlled delay, etc.), it is desired to complete a page eviction (or write in the case of a data write) to Storage #1 410. Depending on how the system is capable of writing to Storage #1 410, Copy 6 may be performed next that may reverse the page eviction from memory class 1. In some cases, actions such as Copy 5 followed by Copy 6 may not necessarily not copy a page back to its original (source) memory location but to a newly released and different (target) location, as shown in FIG. 4 (and thus the temporary eviction may not be necessarily exactly reversed, even though it may help to think of the action as a reversal). In the case that the system always writes pages to memory class 3 (and thus Storage #1 410) from memory class 1 (e.g. due to main memory bus architecture, DMA architecture, etc.), Copy 6 should be performed before a copy such as Copy 7 is performed to complete the page eviction (similarly for a data write). Note that Copy 6, as was the case for Copy 5, may, in certain embodiments, not require Bus #1 and CPU resources.

Copy 7 457 shows the second part of the case (e.g. represents an action performed) in which, for example, a temporary page eviction is reversed (or page eviction completed, etc.). Copy 7 completes a page eviction (or data write) using a copy of an evicted page from memory class 1 to memory Class 3 (and thus to Storage #1 410). In other embodiments, copies directly from memory class 2 to memory class 3 (and thus to Storage #1 410) may be performed and in that case Copy 6 and Copy 7 may be combined into one operation and avoid the need to request or consume etc. any space in memory class 1.

Copy 8 458 is the equivalent to Copy 4 but corresponds to (or performs) a data write to Storage #1 410 rather than a page eviction. In the case of the page eviction, the write (Copy 4) completes to memory class 4 (which is part of VMy 432 and contains the page file) on Storage #1 410. In the case of a data write (Copy 8) the write completes to Storage #1 410 in a region that is outside the VMy.

Copy 9 459 shows the copy of a page to Storage #2 430. Copy 9 may correspond to a data write since in FIG. 4 Storage #2 430 is not part of the VMy (though in other embodiments it may be). In the same way that Copy 5 etc. was used to delay, postpone etc. Copy 3 (applied to a page eviction) the same technique(s) may be used to delay a data write. Thus, for example, instead of performing Copy 9 immediately, the following actions (e.g. under program control, direction of the CPU, direction of the OS, direction of the main memory, in a configurable or dynamic fashion, etc.) may be performed: first perform a Copy 5, second perform a Copy 6, third perform a Copy 9.

Such a delay (or other similar write manipulation, etc.) might be opted for in many situations. For example, in the case described above where Storage #2 430 is remote, possibly on a wireless connection that may be unreliable (e.g. intermittent, etc.) or consumes more power than presently available etc, one may, in some embodiments, opt to temporarily store writes that may then be completed at a later time etc.

In one embodiment, such delayed data writes may be used with techniques such as performing the writes to log files etc. to allow interruptions of connectivity, avoid data corruption, etc.

In another embodiment, data writes may be aggregated (e.g. multiple writes combined into a single write, etc.). Write aggregation may exhibit various optional features including but not limited to: improved bandwidth; reduced power; reduced wear in NAND flash, etc.

In another embodiment, data writes may be combined (e.g. multiple writes to the same location are collapsed together, resulting in many fewer writes). Write combining offers several possible features including but not limited to: reduced NAND flash write amplification (e.g. the tendency of a single data write to an SSD, which may use NAND flash for example, to generate multiple writes internally to the SSD leading to rapid wear out of the NAND flash, etc.); reduced power, improved bandwidth and performance, etc.

FIG. 5

FIG. 5 shows copy operations corresponding to memory writes in a system using main memory with multiple memory classes, in accordance with another embodiment. As an option, the exemplary system of FIG. 5 may be implemented in the context of the architecture and environment of the previous Figure(s), or any subsequent Figure(s). Of course, however, the exemplary system of FIG. 5 may be implemented in the context of any desired environment.

In explaining the copy operations corresponding to memory writes in the context of FIG. 5, optional features will be described that may be achieved using multiple classes in main memory. In FIG. 5, a System 500 includes a CPU 502 coupled to Memory 526 using Bus #1 504, coupled to Storage #1 510 using Bus #2 512, and coupled to Storage #2 530 using Bus #3 532. In FIG. 5 Storage #1 contains Data #1 542. In FIG. 4 Storage #2 530 contains Data #2 540. In FIG. 5, memory class 1 506, memory class 2 508, with memory class 3 534 and memory class 4 536 both located on Storage #1 510 together form VMy 532. In FIG. 5, memory class 1 506 and memory class 2 508 form the Main Memory 538. In FIG. 5, memory class 3 534 forms a cache for Storage #1 510 and Disk #1 544. In FIG. 5, memory class 4 536 located on Storage #1 510 contains the page file. In FIG. 5, memory class 3 534 and memory class 4 536 are not part of Main Memory 538 (but in other embodiments they may be).

In general the copy operations shown in FIG. 5 correspond to operations that generally write to (e.g. in the direction towards, or complete at, etc.) memory class 1 and are thus opposite in their direction to those similar copy operations shown in FIG. 4.

In FIG. 5 various alternative copy operations (Copy 13 553, Copy 14 554, Copy 15 555, Copy 16 556, Copy 17 557, Copy 18 558, Copy 19 559) have been diagrammed. These copy operations perform on various pages (Page 00 580, Page 01 581, Page 02 582, Page 03 583, Page 04 584, Page 05 585, Page 06 586).

It should be noted that, as in the description of FIG. 4, each copy may be: (a) a true copy (e.g. element 1 in location 1 before a copy operation and two elements after a copy operation: element 1 in location 1 and element 2 in location 2, with element 2 being an exact copy of element 1) (b) a move (e.g. element 1 in location 1 before the copy operation, and element 1 in location 2 after the copy operation) (c) copy or move using pointers or other indirection (d) copy with re-location (element 1 in location 1 before the copy operation and two elements after the copy operation: element 1 in location 2 and element 2 in location 3, with element 2 being an exact copy of element 1, but locations 1, 2, and 3 being different).

In some embodiments, a copy of types (a)-(d) may result, for example, from software (or other algorithm, etc.) involved that may not be described in each and every embodiment and that in general may not be relevant to the embodiment description.

These copy operations shown in FIG. 5 will be now described.

Copy 13 553 shows a copy from memory class 3 to memory class 1. This copy could be part of a page fetch or a read for example. Copy 13 uses Bus #1 and Bus #2 as well as CPU resources.

Copy 14 normally precedes Copy 13, but may not always do so. For example, suppose that memory class 3 may act as a cache for Storage #1 510 then Copy 14 may not be required if the page requested is in cache. In the case of Copy 14 the read is from memory class 4. Supposing that memory class 4 536 located on Storage #1 510 contains the page file then Copy 14 and Copy 13 together represent a page fetch. In one embodiment, all pages (or most frequently used pages, etc.) may be kept in memory class 4 536.

Copy 15 copies from memory class 1 to memory class 2 within Main Memory 538. In some embodiments, two page files may be maintained, one on Storage #1 510 and one in memory class 2 (for example memory class 2 may contain more frequently used pages, etc.). In this case, Copy 15 may represent a page fetch from memory class 2. Note that, in contrast to Copy 13, and depending on how the Main Memory is constructed, Copy 15 may not require Bus #1 or CPU resources (or may at least greatly decrease demands on these resources) and alternative embodiments and architectures will be described for Main Memory that have such resource-saving features below.

Copy 16 shows the second part of the case (e.g. represents an action performed) in which, for example, a page is fetched. Depending on how the system is capable of reading from Storage #1 510, Copy 17 may be performed before Copy 16 is performed. Thus in the case that the system always reads pages from memory class 3 (and thus Storage #1 510) to memory class 1 (e.g. due to main memory bus architecture, DMA architecture, etc.) then Copy 17 is performed before a copy such as Copy 16 is performed to complete the page fetch (similarly for a data read). Note that Copy 16, as was the case for Copy 15, exhibits an optional feature, that in certain embodiments the copy may not require Bus #1 and CPU resources.

Copy 17 shows the first part of the case (e.g. represents an action performed) in which, for example, a page is fetched. Copy 17 performs a page fetch using a copy of a requested page from memory class 3 to memory Class 1 (and thus from Storage #1 510). In other embodiments a copy may be performed directly to memory class 2 from memory class 3 (and thus from Storage #1 510) and in that case Copy 16 and Copy 17 may be combined into one operation and the need to request or consume etc. any space in memory class 1 may be avoided.

Copy 18 is the equivalent to Copy 14 but corresponds to (or performs) a data read from Storage #1 510 rather than a page fetch. In the case of the page fetch, the read (Copy 14) reads from memory class 4 (which is part of VMy 532 and contains the page file). In the case of a data read (Copy 18) the read is from Storage #1 510 in a region that is outside the VMy.

Copy 19 shows the copy of a page from Storage #2 530. Copy 19 may correspond to a data read since in FIG. 5 Storage #2 530 is not part of the VMy (though in other embodiments it may be). In the case described above where Storage #2 530 is remote, possibly on a wireless connection that may be unreliable (e.g. intermittent, etc.) or consumes more power than presently available etc, one may, in some embodiments, opt to temporarily (or permanently, for a certain period of time, etc.) store data in memory class 2 that would otherwise need to be read over an unreliable link. In one embodiment such caching may be used with techniques such as monitoring data use etc. to allow interruptions of connectivity, avoid data corruption, etc. For example, suppose a user fetches maps on a cell phone via a wireless connection. This would involve operations such as Copy 19. The map data may then be stored (using copy operations already described in FIG. 4 for example) in memory class 2. If the wireless connection is interrupted, map data may then be read from memory class 2 (using operations such as Copy 15 for example). In other embodiments data may also be stored (or instead be stored, in a configurable manner be stored, dynamically be stored, under program control be stored, etc.) in Storage #1 510.

FIG. 6

FIG. 6 shows a method 600 for copying a page between different classes of memory, independent of CPU operation, in accordance with another embodiment. As an option, the method 600 may be implemented in the context of the architecture and environment of the previous Figures, or any subsequent Figure(s). Of course, however, the method 600 may be carried out in any desired environment. It should also be noted that the aforementioned definitions may apply during the present description.

As shown, a first instruction is received, the first instruction being associated with a copy operation. See operation 602. The first instruction may include any instruction or instructions associated with a copy command or being capable of initiating a copy command or operation. For example, in various embodiments, the first instruction may include one or more copy operations, one or more read instructions associated with at least one copy command, one or more write commands associated with at least one copy operation, various other instructions, and/or any combination thereof.

In response to receiving the first instruction, a first page of memory is copied to a second page of memory, where at least one aspect of the copying of the first page of memory to the second page of memory is independent of at least one aspect of a CPU operation of a CPU. See operation 604. In the context of the present description, a page of memory refers to any fixed-length block of memory that is contiguous in virtual memory.

In operation, an apparatus including a physical memory sub-system may be configured to receive the first instruction and copy the first page of memory to the second page of memory. In one embodiment, the first page of memory may be copied to the second page of memory while the CPU is communicatively isolated from the physical memory sub-system. In the context of the present description, being communicatively isolated refers to the absence of a signal (e.g. an electrical signal, a control and/or data signal, etc.) at a given time. In one embodiment, the apparatus may be configured such that the communicative isolation includes electrical isolation (e.g. disconnect, switched out, etc.).

In another embodiment, the physical memory sub-system may include logic for executing the copying of the first page of memory to the second page of memory, independent of at least one aspect of the CPU operation. For example, the first page of memory may be copied to the second page of memory, independent of one or more CPU copy operations. As another example, the first page of memory may be copied to the second page of memory, independent of one or more CPU write operations. In still another embodiment, the first page of memory may be independently copied to the second page of memory, by accomplishing the same without being initiated, controlled, and/or completed with CPU instructions.

In still another embodiment, the physical memory sub-system may include at least two classes of memory. As an option, the first page of memory may be resident on a first memory of a first memory class, and the second page of memory may be resident on a second memory of a second memory class. In this case, the logic may be resident on the first memory of the first memory class and/or on the second memory of the second memory class. In another embodiment, the logic may be resident on a buffer device separate from the first memory and the second memory.

As noted, in one embodiment, a first page of memory may be copied to a second page of memory, where at least one aspect of the copying of the first page of memory to the second page of memory being independent of at least one aspect of a central processing unit (CPU) operation of a CPU. In various embodiments, different aspects of the copying may be independent from the CPU operation. For example, in one embodiment, reading of the first page of memory may be independent of a CPU operation. In another embodiment, a writing of the second page of memory may be independent of a CPU operation. In either case, as an option, the at least one aspect of the CPU operation may include any operation subsequent to an initiating instruction of the CPU that initiates the copying.

The copying may be facilitated in different ways. For example, in one embodiment, a buffer device (e.g. logic chip, buffer chip, etc.) may be configured to participate with the copying. The buffer device may be part of the physical memory sub-system or separate from the physical memory sub-system.

In one embodiment, the first instruction may be received via a single memory bus. For example, the physical memory sub-system 1A-102 of FIG. 1A may include the first page of memory and the second page of memory. In this case, the first instruction may be received via the single memory bus 1A-108.

More illustrative information will now be set forth regarding various optional architectures and features with which the foregoing techniques discussed in the context of any of the present or previous figure(s) may or may not be implemented, per the desires of the user. For instance, various optional examples and/or options associated with the operation 602, the operation 604, and/or other optional features have been and will be set forth in the context of a variety of possible embodiments. It should be strongly noted that such information is set forth for illustrative purposes and should not be construed as limiting in any manner. Any of such features may be optionally incorporated with or without the inclusion of other features described.

FIG. 7

FIG. 7 shows a system using with multiple memory classes, where all memory is on one bus, in accordance with another embodiment. As an option, the exemplary system of FIG. 7 may be implemented in the context of the architecture and environment of the previous Figure(s), or any subsequent Figure(s). Of course, however, the exemplary system of FIG. 7 may be implemented in the context of any desired environment.

In FIG. 7, a System 700 includes a CPU 702 coupled to Memory 726 and coupled to Storage #1 710 using Bus #1 704. In FIG. 7, memory class 1 706, memory class 2 708, with memory class 3 734 and memory class 4 736 both located on Storage #1 710 together form VMy 744. In FIG. 7, memory class 3 734 forms a cache for Storage #1 710. In FIG. 7, memory class 4 736, located on Storage #1 710, contains the page file.

In one embodiment, the copy operations shown in FIG. 7 may, in one embodiment, correspond to operations shown in FIG. 4 and in FIG. 5. Note that the copy operations in FIG. 7 use double-headed arrows to simplify the diagram, but any single copy operation may perform its operation in one direction.

In FIG. 7 there is just one single bus, Bus #1 704, for the CPU to access the entire VMy. In FIG. 7 there may be other changes to memory and main memory.

In FIG. 4 and in FIG. 5, main memory and memory were equivalent. In FIG. 7 they may not necessarily be equivalent. In FIG. 7, Memory 726 includes Main Memory 738 as a subset. In FIG. 7, Memory 726 includes VMy 744 as a subset.

In one embodiment, main memory (e.g. primary memory, primary storage, internal memory, etc.) may include memory that is directly accessible to the CPU. In FIG. 7, for example, memory class 3 734 and memory class 4 736 (which may be part of secondary storage in various alternative embodiments) may now be considered part of main memory (and thus not as drawn in FIG. 7). In the context of the present description, this may be refer to as “Embodiment A” of main memory. In FIG. 7, in Embodiment A, main memory would then comprise memory class 1 706, memory class 2 708, memory class 3 734 and memory class 4 736. In FIG. 7, in the context of Embodiment A, VMy 744 would then be the same as main memory.

In an alternative Embodiment B of main memory, the role of memory class 3 734 in FIG. 7 may be considered as cache, and memory class 4 736 in FIG. 7 as storage, and thus not part of Main Memory 738. In Embodiment B, Main Memory 738 comprises memory class 1 706 and memory class 2 708.

In an alternative Embodiment C of main memory, one could take into consideration the fact that main memory is equivalent to primary storage and thus reason that anything equivalent to secondary storage is not main memory. With this thinking, main memory may, in one embodiment, include M1 only, and M2 is equivalent to secondary storage. In Embodiment C, only memory class 1 706 in FIG. 7 would be main memory.

In FIG. 7, Embodiment B is adopted. FIG. 7 has been used to point out the difficulty of using the term main memory in systems such as that shown in FIG. 7. In embodiments where there is the possibility of confusion, use of the term main memory has been avoided.

In one embodiment, memory may include the PM coupled to the CPU. In such embodiment of FIG. 7, Memory 726 is the memory coupled to the CPU 702. Note that in some embodiments not all memory classes that make up Memory 726 may be equally coupled to the CPU (e.g. directly connected, on the same bus, etc.), but they may be. Thus, Memory 736 in FIG. 7 comprises: memory class 1 706 (M1); memory class 2 708 (M2); memory class 3 734 (M3); memory class 4 736 (M4); and Data #1 742 (D1).

In one embodiment, VMy 744 may include the memory space available to the CPU. In such embodiment (in the context of FIG. 7), VMy 744 may be the memory space available to the CPU 702.

Note that in some embodiments CPU 702 may be coupled to Storage #2 730 using Bus #2 732 as shown in FIG. 7. In FIG. 7, Storage #2 730 contains Data #2 740. In FIG. 7 Storage #2 730 may now be the only Secondary Storage 746, since now Storage #1 710 is part of Memory 726.

In one embodiment, Storage #2 730 may be used to store various Data #2 740 (e.g. overlays, code, software, database, etc.). In some embodiments, System 700 may be a consumer device, Bus #2 732 may include a wireless connection, Storage #2 730 may be cloud storage used to store data (e.g. overlays, code, software, database, etc.). For example, information (e.g. data, program code, overlay blocks, data, database, updates, other software components, security updates, patches, OS updates, etc.) may be fetched remotely from Storage #2 730 [e.g. as an application (e.g. from an application store, operating in demo mode, purchased but accessed remotely, rented, monitored, etc.); as a transparent download; via a push model; via a push model; etc.].

If Storage #2 730 (if present) is detached, then all CPU I/O may then performed over Bus #1 704. The basic model of VMy 744 with storage and data has not changed, and thus may require little change to software (e.g. OS, applications, etc.) and/or CPU (and/or CPU components, e.g. MMU, page tables, TLB, etc.). This is one possible feature of the system architecture when implemented as that shown and described in the embodiment of FIG. 7. There are other possible features, as well. One example is that the elimination of one or more CPU, I/O or other buses may provide cost savings in a system (e.g. through reducing pins per package and thus cost, reducing package size and thus package cost, reduced PCB area and thus cost, reduced PCB density and thus cost, etc.), power (e.g. through reduced numbers of high-power bus drivers and receivers, etc.), and space savings (e.g. through smaller packages, smaller PCB, less wiring, etc.). Yet another possible feature is that System 700 now may only need to handle read/write data traffic between CPU and Main Memory on Bus #1 704. All other data traffic (e.g. paging, overlay, caching and other data transfer functions in VMy etc.) may be handled independently, thus freeing resources required by Bus #1 704 and CPU 702. As shown in FIG. 7, none of the arrows representing data traffic (e.g. move, copy etc.) involve I/O Bus#1 704. This offers further savings in cost by potentially decreasing demands on a critical part of the system (e.g. Bus #1 704 and CPU 702, etc.). It should be noted now that in a system where the memory components may be specially designed and packaged etc. (e.g. for consumer electronics, cell phones, media devices, etc.) it may be cheaper (and easier) to perform these functions in the memory system (e.g. design in, integrate, co-locate, etc.) than to use expensive CPU resources, increase CPU die area, add extra CPU pins, create larger CPU packages, etc.

In FIG. 7, Bus #1 704 is drawn to diagrammatically suggest and logically represent embodiments that include, but are not limited to, the following alternatives: (a) Bus #1 704 may be a JEDEC standard memory bus (large arrow) with possibly modified control signals drawn separately as Bus #1 Control 748 (small arrow). The control signals in Bus #1 Control 748 may be JEDEC standard signals, modified JEDEC standard signals, multiplexed signals, additional signals (e.g. new signals, extra signals, multiplexed signals, etc.), re-used or re-purposed signals, signals logically derived from JEDEC standard signals, etc; (b) Bus #1 704 may be wider than a standard JEDEC memory bus (e.g. 128, 256, or 512 bits etc. of data, wider address bus, etc.). This type of embodiment, with high-pin count data buses, makes sense because one or more I/O buses may not be present, for example in systems that package main memory with CPU; (c) Bus #1 704 may be a combination of I/O bus and memory bus, and may share data and/or address signals between buses and may use shared, separate, or new control signals (including JEDEC standard signals, signals derived from JEDEC standard signals, or non-standard signals, etc.) for different memory classes. In the context of the present description, this bus may be referred to as a hybrid bus; (d) Bus #1 704 may be a new standard or proprietary bus that may be customized for an application (e.g. stacked CPU and memory die in a cell phone etc.). For example, a packet-switched bus, a split-transaction bus, etc; (e) combinations of these.

Note that though, in FIG. 7, Bus #1 704 is shown separately from Bus #1 Control 748, various terms such as the bus, or the memory bus, or Bus #1, etc. may refer to Bus #1 704 although all elements of Bus #1 may be included, including the control signals, Bus #1 Control 748, for example. In some embodiments, components of the bus may be called out individually, such as when one component of the bus (e.g. data, address, etc.) may be standard (e.g. JEDEC, etc.) but another component of the bus (e.g. control, etc.) may be modified (e.g. non-standard, etc.).

FIG. 8

FIG. 8 shows a system with three classes of memory on one bus, in accordance with another embodiment. As an option, the exemplary system of FIG. 8 may be implemented in the context of the architecture and environment of the previous Figure(s), or any subsequent Figure(s). Of course, however, the exemplary system of FIG. 8 may be implemented in the context of any desired environment.

In FIG. 8, a System 800 includes a CPU 802 coupled to Memory 826 and coupled to Storage #1 810 using Bus #1 804 and Bus # Control 848. In FIG. 8, memory class 1 806 (M1), memory class 2 808 (M2), with memory class 3 834 (M3) located on Storage #1 810 together form VMy 832. In FIG. 8, Storage #1 810 contains Data #1 842. Note that there is just one bus, Bus #1 804, for the CPU to access the entire VMy. In FIG. 8, memory class 3 834, located on Storage #1 810, contains the page file. In one embodiment, the copy operations shown in FIG. 8 may correspond to copy operations shown in and described with regard to FIG. 4 and FIG. 5, and that were also shown in FIG. 7. In the embodiment of FIG. 8 there is no secondary storage shown, though in different embodiments there may be secondary storage.

FIG. 9

FIG. 9 shows a system with multiple classes and multiple levels of memory on one bus, in accordance with another embodiment. As an option, the exemplary system of FIG. 9 may be implemented in the context of the architecture and environment of the previous Figure(s), or any subsequent Figure(s). Of course, however, the exemplary system of FIG. 9 may be implemented in the context of any desired environment.

In FIG. 9, a System 900 includes a CPU 902 coupled to Memory 926 using Bus #1 904 and Bus #1 Control 948. In the embodiment of FIG. 9, there may not be secondary storage, though in different embodiments there may be secondary storage.

There are some differences in the block diagram of the embodiment shown in FIG. 9 from previous embodiments even though the functions of previous embodiments are still present: (a) there is no distinction in memory class C2 908 between cache, storage, etc. (b) In FIG. 9, both M2 and M3 are shown present in the same class of memory. The term levels of memory will be used to describe the functionality. For example, it may be said that level M2 and level M3 are both present in the same class (c) The VMy is not explicitly shown in FIG. 9. Instead, the boundary of VMy is capable of changing. For example, at one point in time VMy may be equal to VMy1 932, at another point in time VMy may be equal to VMy2 934, etc.

In FIG. 9, VMy1 932 comprises memory level B1.M.C1 956 in memory class C1 906 plus memory level B1.M2.C2 950 in memory class C2 908.

In FIG. 9, VMy2 934 comprises memory level B1.M.C1 956 in memory class C1 906 plus memory level B1.M2.C2 950 in memory class C2 908 plus memory level B1.M3.C2 954 in memory class C2 908.

In other embodiments the VMy may be extended between classes. Thus, for example, although M3 is shown as being in C2 for simplicity (and perhaps no real difference between M2 and M3 as far as technology is concerned in FIG. 9), it can be seen that in other embodiments M3 may be in another memory class, C3 for example (not shown in FIG. 9).

In other embodiments, VMy may be moved between classes. For example, in FIG. 9, VMy2 is shown as being VMy1 (which is M1 plus M2) plus an additional portion of C2 (or plus an additional portion of C3 as just described etc.). Similarly, VMy3 may be M1 plus M3. Thus, changing between VMy1 and VMy3 moves a portion of VMy from M2 to M3. If M3 is a different memory class from M2, the change from VMy1 to VMy3 is equivalent to moving a portion of VMy between memory classes.

In FIG. 9, a portion of memory class C2 908 contains Data #1 942, where that portion is B1.D1.C2 952. Of course, in other embodiments, different levels of data (e.g. D2, D3, etc.) may be present in a similar fashion to the different levels of memory (e.g. M1, M2, M3, etc.). However, in the current embodiment, the distinction between memory and data is just that of the difference between format that data is normally stored in a memory system and the format that data is normally stored in a storage system (e.g. on disk using a filesystem, etc.).

In FIG. 9, memory class C2 908 may contain the page file. In one embodiment, the copy operations shown in FIG. 9 may correspond to copy operations shown in and described with regard to FIG. 4 and FIG. 5, and that were also shown in FIG. 7 and FIG. 8. In the embodiment, there may be no secondary storage, although in different embodiments there may be secondary storage.

FIG. 10

FIG. 10 shows a system with integrated memory and storage using multiple memory classes, in accordance with another embodiment. As an option, the exemplary system of FIG. 10 may be implemented in the context of the architecture and environment of the previous Figure(s), or any subsequent Figure(s). Of course, however, the exemplary system of FIG. 10 may be implemented in the context of any desired environment.

One aspect of embodiments such as that shown in FIG. 10 is the reduction of the number of wasted I/O accesses requiring the memory bus. In those embodiments where memory may perform many, most or all system I/O functions, performance is greatly enhanced. Thus, in FIG. 10, the embodiment of System 1000 moves more I/O functions into memory. In this way, traffic over the high-speed memory bus is reduced, e.g. reduced to just the essential traffic between CPU and memory, etc.

Another aspect of embodiments such as that shown in FIG. 10 is that all VMy functions are now contained in a single memory.

In FIG. 10, system 1000 contains a CPU 1002. In FIG. 10, CPU 1002 is coupled to Memory (in FIG. 10) using Bus #1 (in FIG. 10). In FIG. 10 CPU 1002 is optionally coupled to Disk (in FIG. 10) using Bus #2 (in FIG. 10). In FIG. 10, the Memory comprises memory class 1 (in FIG. 10) and memory class 2 (in FIG. 10). In FIG. 10, memory class 2 comprises: memory level M2 (in FIG. 10); memory level M3 (in FIG. 10) used as a Page File Cache (in FIG. 10); memory level M4 (in FIG. 10) used as a Page File RAM Disk (in FIG. 10); memory level D1 (in FIG. 10) used as a Data RAM Disk (in FIG. 10).

In one embodiment, a RAM disk may include software (e.g. a software driver, Microsoft Windows .dll file, etc.) used to perform the functions of a small disk in memory (e.g. emulate a disk, etc.). A RAM disk may be used (e.g. in an embedded system, for data recovery, at boot time, etc.) to implement small but high-speed disks, etc. A RAM Disk may be implemented using any combination of memory, software, etc. and does not have to include RAM and does not have to perform conventional disk functions.

The use of one or more RAM disks in System 1000 is purely for convenience of existing software, hardware and OS design. For example, most OS use a disk for the page file. If a portion of memory is used to emulate a disk, it may be easier for the OS to use that portion of memory for a page file and swap space without modification of the OS.

For example, systems using an OS (e.g. Microsoft Windows, Linux, other well as other OS, etc.) may require a C drive (in FIG. 10) (or equivalent in Linux etc.) to hold the OS files (e.g. boot loader, etc.) and other files required at boot time. In one embodiment, memory class 2 (or a portion of it) may be non-volatile memory to provide a C drive. In another embodiment, memory class 2 may be a volatile memory technology but backed (e.g. by battery, supercapacitor, etc.). In other embodiments, memory class 2 may be a volatile memory technology but contents copied to a different memory class that is non-volatile on system shut-down and restored before boot for example.

In FIG. 10, the Data RAM disk is assigned drive letter C, the Page File RAM disk is assigned drive letter D (in FIG. 10), the Page File Cache is assigned letter E (in FIG. 10), and the (optional) Disk is assigned drive letter F (in FIG. 10).

In FIG. 10, the use of a separate Page File Cache in memory may be compatible with existing cache systems (e.g. ReadyBoost in Microsoft Windows, etc.).

As shown the disks C, D and E are accessible independently over I/O Bus #1. In FIG. 10, the disk D is dedicated as a page file and contains the page file and is used as swap space. In other embodiments, the CPU 1002 may use data disk C as well as or instead of D for page files (e.g. swap space, etc.).

In the context of the present description, Microsoft Windows drive letters (e.g. volume, labels, etc.) have been utilized, such as C and D etc., for illustrative purposes, to simplify the description and to more easily and clearly refer to memory regions used for data, memory regions used for swap space, etc. For example, these regions (e.g. portions of memory, etc.) may equally be labeled as /data and /swap in Linux, etc. Of course, other similar functions for different regions of memory etc. may be used in a similar fashion in many other different types and versions of operating systems.

It should be noted that the number, location and use of the memory regions (e.g. C, D, etc.) may be different from that shown in FIG. 10 or in any other embodiment without altering the essential functions. In some embodiments, one may separate the page file and swap space from data space as this may improve VMy performance. In other embodiments, swap space and data space may be combined (e.g. to reduce cost, to simplify software, reduce changes required to an OS, to work with existing hardware, etc.).

FIG. 10 shows system 1000 using a Page File Cache. In FIG. 10, the Page File Cache may be used for access to the Page File RAM Disk. In some embodiments, the Page File Cache may not be present and the CPU may access the Page File RAM Disk directly.

The internal architecture of the Memory will be described in detail below but it should be noted that in various embodiments of the system shown in FIG. 10: (a) C and D may be on the same bus internal to the Memory, with E on a separate bus (b) D and E may be on the same bus, with C on a separate bus, (c) other similar permutations and/or combinations, etc.

In other alternative embodiments (e.g. for a cell phone, etc.), some data (e.g. additional VMY, database, etc.) may be stored remotely and accessed over a wired or wireless link. Such a link (e.g. to remote storage etc.) is indicated by the optional (as indicated by dotted line(s) in FIG. 10) Bus #2 and optional Disk #1 in FIG. 10.

It should be noted that not all of C, D and E have to be in memory class 2. For example, any one more, combination, or all of C, D and E may be in memory class 1 or other memory class (not shown in FIG. 10, but that may be present in other embodiments etc.), etc.

It should be noted that C, D and E functions may move (e.g. migrate, switch, etc.) between memory class 1 and memory class 2 or any other memory class (not shown in FIG. 10, but that may be present in other embodiments etc.).

In some embodiments, Data RAM Disk C may be included as well as optional Disk F (e.g. HDD, SSD, cloud storage etc.) because Disk F may be larger and cheaper than a RAM disk.

In some embodiments, the OS may be stored on a disk F (e.g. permanent media, etc.) rather than a volatile RAM disk, for example.

FIG. 11

FIG. 11 shows a memory system with two memory classes containing pages, in accordance with another embodiment. As an option, the exemplary system of FIG. 11 may be implemented in the context of the architecture and environment of the previous Figure(s), or any subsequent Figure(s). Of course, however, the exemplary system of FIG. 11 may be implemented in the context of any desired environment.

FIG. 11 shows a Memory System 1100 with Memory 1102. Memory 1102 comprises pages distributed between M1.C1 1104 and M2.C2 1106.

In FIG. 11, memory M1.C1 1104 e.g. level M1 memory of memory class C1 (e.g. DRAM in some embodiments, SRAM in some embodiments, etc.) may have a capacity of N pages (e.g. Page 1 1108, Page 2, etc., Page N 1110) as shown in FIG. 11. M1.1 may be a few gigabytes in size.

In FIG. 11, memory M2.C2 1106 [e.g. level M2 memory of memory class C2 (e.g. DRAM in some embodiments if M1 is SRAM, NAND flash in some embodiments if M1 is DRAM, etc.] may have a larger capacity than M1 of M pages (e.g. Page 1 1112, Page 2, etc., Page M 1114) as shown in FIG. 11. In some embodiments, M2.C2 may be several terabytes or larger in size.

In one embodiment, a page size may be 4 kB. A 4 GB memory system could then hold up to 1M pages. In the 2011 timeframe a disk that is part of secondary storage and normally used to hold a page file as part of VMy may hold up to 2TB. Thus, the disk may hold up to 2TB/4 kB or 500M pages. It may be desirable to at least match that capability in a system such as FIG. 11 using multiple memory classes. Such a large memory capacity may be useful, for example, to hold very large in-memory databases or multiple virtual machines (VMs).

One potential issue is how to address such a large memory. A standard JEDEC DDR memory address bus may not have enough address bits to address all available memory (e.g. a standard memory address bus is not wide enough).

The potential addressing issue is similar to an office building having four incoming phone lines or circuits but eight office phones. Suppose are four incoming phone numbers. This potential issue may be solved by giving each office phone an extension number. Four phone numbers may address eight phone extension numbers, but with the limitation that only four extensions can be used at any one time. The four incoming phone numbers provide a continuously changing window to the eight extension numbers.

FIG. 11 shows one embodiment that allows the addressing of a memory M2 using an address bus that is too narrow (e.g. too few bits). The Inset 1116 shows the contents of a single look-up table at two points in time, Table 1118 and Table 1120. At time t1 Table 1118 provides a mapping between address in M1 and corresponding addresses in M2. For simplicity, in Table 1118 only four addresses are shown for M1 (though there are N). These four addresses map to four addresses in M2. At time t1 address 1 in M1 maps to address 5 in M2, etc. At time t2 the mapping changes to that shown in Table 1120. Note that now address 1 in M1 corresponds to address 3 in M2.

Thus, four pages in M1.C1 1104, Pages 1148 are effectively mapped to eight pages in M2.C2 1106, Pages 1144.

In different embodiments (a) the CPU and VMM including page tables, etc. may be used to handle the address mapping; (b) logic in the memory system may be used; (c) or both may be used.

In the current embodiment, the page (memory page, virtual page) may include a fixed-length or fixed size block of main memory that is contiguous in both PM addressing and VMy addressing. A system with a smaller page size uses more pages, requiring a page table that occupies more space. For example, if a 2^32 virtual address space is mapped to 4 kB (2^12 bytes) pages, the number of virtual pages is 2^20 (=2^32/2^12). However, if the page size is increased to 32 KB (2^15 bytes), only 2^17 pages are required. The current trend is towards larger page sizes. Some instruction set architectures can support multiple page sizes, including pages significantly larger than the standard page size of 4 kB.

Starting with the Pentium Pro processor, the IA-32 (x86) architecture supports an extension of the physical address space to 64 GBytes with a maximum physical address of FFFFFFFFFH. This extension is invoked in either of two ways: (1) using the physical address extension (PAE) flag (2) using the 36-bit page size extension (PSE-36) feature (starting with the Pentium III processors). Starting with the Intel Pentium Pro, x86 processors support 4 MB pages using Page Size Extension (PSE) in addition to standard 4 kB pages. Processors using Physical Address Extension (PAE) and a 36-bit address can use 2 MB pages in addition to standard 4 kB pages. Newer 64-bit IA-64 (Intel 64, x86-64) processors, including AMD's newer AMD64 processors and Intel's Westmere processors, support 1 GB pages.

Intel provides a software development kit (SDK) PSE36 that allows the system to use memory above 4 GB as a RAM disk for a paging file. Some Windows OS versions use an application programming interface (API) called Address Windowing Extensions (AWE) to extend memory space above 4 GB.

AWE is a set of Microsoft APIs to the memory manager functions that enables programs to address more memory than the 4 GB that is available through standard 32-bit addressing. AWE enables programs to reserve physical memory as non-paged memory and then to dynamically map portions of the non-paged memory to the program's working set of memory. This process enables memory-intensive programs, such as large database systems, to reserve large amounts of physical memory for data without necessarily having to be paged in and out of a paging file for usage. Instead, the data is swapped in and out of the working set and reserved memory is in excess of the 4 GB range. Additionally, the range of memory in excess of 4 GB is exposed to the memory manager and the AWE functions by PAE. Without PAE, AWE cannot necessarily reserve memory in excess of 4 GB.

OS support may, in some embodiment, also required for different page sizes. Linux has supported huge pages since release 2.6 using the hugetlbfs filesystem. Windows Server 2003 (SP1 and newer), Windows Vista and Windows Server 2008 support large pages. Windows 2000 and Windows XP support large pages internally, but are not exposed to applications. Solaris beginning with version 9 supports large pages on SPARC and the x86. FreeBSD 7.2-RELEASE supports superpages.

As costs and performance of the memory technologies vary (e.g. DRAM, flash, disk), then the capacities allocated to different memory levels, M1, M2 etc, may change.

In the embodiment shown in FIG. 11 it may be desirable to allow: (a) the CPU to address and read/write from/to memory M1.C1 1104 and from/to memory M2.C2 1106; (b) to perform copy operations between M1 and M2 (and between M2 and M1); (c) perform table updates etc; (d) send and receive status information etc. In the embodiment of FIG. 11, three simple commands are shown that may be sent from CPU to Memory 1102: RD1 1124; CMD1 1126; WR1 1128.

In FIG. 11, at time t1 command RD1 1124 from the CPU performs a read from Page a 1146. If Page a is already in M1.C1 1104 the read completes at t2. If not, then Page d is fetched via an operation shown as Read 1130 from Page d 1138 and the read completes at t3. The embodiments described below will describe how the memory bus may handle read completions that may occur at variable times (e.g. either at t2 or at t3, etc.). It should be noted now that several embodiments are possible, such as: (a) one embodiment may use a split-transaction bus (e.g. PCI-E, etc.); (b) another embodiment may use a retry signal; (c) another embodiment may exchange status messages with the CPU; (d) a combinations of these, etc.

In FIG. 11, at time t4 command CMD1 1124 from the CPU initiates an operation etc. Suppose that CMD1 is a Swap 1132 operation. Then Page b 1147 in M1.C1 1104 and Page e 1140 in M2.C2 1106 are swapped as shown in FIG. 11. The embodiments described below describe how logic in Memory 1102 may perform such operations (e.g. swap operation(s), command(s), etc.). It should be noted that such commands may include: updating tables in M1.C1 1104; updating tables in M2.C2 1106; updating tables in logic of Memory 1102; operations to swap, move, transfer, copy, etc; operations to retrieve status from Memory 1102; etc.

In FIG. 11, at time t5 command WR1 1124 from the CPU performs a write to Page c 1150. Depending on how addressing is handled, in one embodiment for example, a table such as Table 1120 may then be read by logic in Memory 1102. As a result of the mapping between addresses in M1 and addresses in M2, a further operation Write 1134 from page c 1150 in M1.C1 1104 to Page f 1142 in M2.C2 1106.

FIG. 12

FIG. 12 shows a memory system with three memory classes containing pages, in accordance with another embodiment. As an option, the exemplary system of FIG. 12 may be implemented in the context of the architecture and environment of the previous Figure(s), or any subsequent Figure(s). Of course, however, the exemplary system of FIG. 12 may be implemented in the context of any desired environment.

FIG. 12 shows a Memory System 1200 with Memory 1202. Memory 1202 comprises pages distributed between M1.C1 1204 , M2.C2 1206 , and M3.C3 1208

In FIG. 12, memory M1.C1 1204 [e.g. level M1 memory of memory class C1 (e.g. SRAM in some embodiments, embedded DRAM in some embodiments, etc.)] may have a capacity of N pages (e.g. Page 1 1210, Page 2, etc., to Page N 1212) as shown in FIG. 11. In one embodiment, M1.1 may be a few megabytes in size.

In FIG. 12, memory M2.C2 1206 [e.g. level M2 memory of memory class C2 (e.g. DRAM in some embodiments if M1 is embedded DRAM, NAND flash in some embodiments if M1 is DRAM, etc.)] may have a larger capacity than M1 of M pages (e.g. Page 1 1214, Page 2, etc., to Page M 1216) as shown in FIG. 11. In some embodiments, M2.C2 may be a few gigabytes or larger in size.

In FIG. 12, memory M3.C3 1208 (e.g. level M3 memory of memory class C3 (e.g. NAND flash in some embodiments if M1 is SRAM, M2 is DRAM, etc.) may have a much larger capacity than M2 of P pages (e.g. Page 1 1218, Page 2, . . . , to Page P 1220) as shown in FIG. 11. In some embodiments, M3.C3 may be many gigabytes in size or even much larger (e.g. terabytes, etc.) in size.

In FIG. 12, operations that may be performed in one embodiment are shown: Operation 1221; Operation 1222; Operation 1223; Operation 1224; Operation 1225; Operation 1226; Operation 1227; Operation 1228.

In FIG. 12, Operation 1221 corresponds to a read R1 from the CPU. If M1 is acting as a DRAM cache (e.g. M1 may be SRAM, and M2 DRAM, etc.), for example, then Page a may be read from M1 if already present. If not then Page b is fetched from M2.

In FIG. 12, Operation 1222 corresponds to a write W1 from the CPU. Page c may be written to M1 and then copied to Page d in M2.

In FIG. 12, Operation 1223 corresponds to a read R2 from the CPU of Page e from M2 where Page e is already present in M2.

In FIG. 12, Operation 1224 corresponds to a write W2 from the CPU to Page f of M2. Depending on the embodiment, Page f may be copied to Page g in M1 so that it may be read faster in future; Page f may also be copied (and/or moved) to Page h in M3.

In FIG. 12, Operation 1225 corresponds to a command C2 from the CPU to copy or move etc. Page i in M3 to Page j in M2. In one embodiment, this may be a CPU command that prepares M2 for a later read of Page j.

In FIG. 12, Operation 1226 corresponds to a command C3 from the CPU to copy Page k in M3 to Page m in M1. This may in some embodiments be a CPU command that prepares M1 for a later read of Page m.

In FIG. 12, Operation 1227 corresponds to a swap of Page n and Page o in M3 initiated without CPU command. In certain embodiments that use NAND flash technology etc. for M3, this may be to provide wear-leveling etc.

In FIG. 12, Operation 1228 corresponds to a swap of Page p and Page q in M3 initiated by CPU command C4. In certain embodiments, that use NAND flash technology etc. for M3 this may be to provide wear-leveling under CPU (or OS etc.) control etc.

FIG. 13

FIG. 13 shows a memory system with three memory classes containing memory pages and file pages, in accordance with another embodiment. As an option, the exemplary system of FIG. 13 may be implemented in the context of the architecture and environment of the previous Figure(s), or any subsequent Figure(s). Of course, however, the exemplary system of FIG. 13 may be implemented in the context of any desired environment.

FIG. 13 shows a Memory System 1300 with Memory 1302. Memory 1302 comprises pages distributed between M1.C1 1304 , M2.C2 1306 , and M3.C3 1308.

In FIG. 13, memory M1.C1 1304 [e.g. level M1 memory of memory class C1 (e.g. SRAM in some embodiments, embedded DRAM in some embodiments, etc.)] may have a capacity of N pages. M1.1 may be a few megabytes in size.

In FIG. 13, memory M2.C2 1306 (e.g. level M2 memory of memory class C2 (e.g. DRAM in some embodiments if M1 is embedded DRAM, NAND flash in some embodiments if M1 is DRAM, etc.) may have a larger capacity than M1 of M pages.

In FIG. 13, memory C3 1308 [e.g. memory class C3 (e.g. NAND flash in some embodiments if M1 is SRAM, M2 is DRAM, etc.)] may have a much larger capacity than M2 of P pages. In some embodiments, M3.C3 may be a many gigabytes or even much larger (terabytes) in size. In the embodiment of FIG. 13 memory C3 1308 is partitioned into M3.C3 1310 and D1.C3 1312. The structure of M3.C3 1310 is memory pages managed by the VMM. The structure of D1.C3 1312 may also be pages but managed by the filesystem (e.g. of the OS. etc.). Thus D1 may be thought of as a disk in memory or RAM disk.

The Inset 1316 shows the contents of a single table at two points in time, Table 1318 and Table 1320. At time t1 Table 1318 is a list (e.g. inventory, pointers, etc.) of pages in M3 and pages in D1. For simplicity in Table 1318 only a few pages are shown for M3 (though there are P pages in M3) and for D1 (though there are F pages in D1). At time t1 there are four pages in M3 (1, 2, 3, 4) and four pages in D1 (5. 6. 7. 8), etc. Suppose the Memory 1302 receives a command CX 1314 that would result in a page being copied or moved from M3 to D1. An example of such a command would be a write from memory M3 to the RAM disk D1. In order to perform that operation Table 1318 may be updated. Suppose Memory 1302 receives a command or commands CY 1330 that would result in a page being copied or moved from M3 to D1 and a page being moved or copied from D1 to M3. Again, examples would be a read/write to/from M3 from/to D1. Again, in one embodiment, these operations may be performed by updating Table 1318. Table 1320 shows the results. At time t2 there are three pages in M3 (1, 2, 8) and five pages in D1 (3, 4, 5. 6), etc. In one embodiment, these operations may be performed without necessarily moving data. In this case, the boundaries that define M3 and D1 may be re-organized.

FIG. 14

FIG. 14 shows a multi-class memory apparatus 1400 for dynamically allocating memory functions between different classes of memory, in accordance with one embodiment. As an option, the apparatus 1400 may be implemented in the context of the architecture and environment of the previous Figures, or any subsequent Figure(s). Of course, however, the apparatus 1400 may be implemented in the context of any desired environment. It should also be noted that the aforementioned definitions may apply during the present description.

As shown, a physical memory sub-system 1402 is provided. In various embodiments, the physical memory sub-system 1402 may include a monolithic memory circuit, a semiconductor die, a chip, a packaged memory circuit, or any other type of tangible memory circuit. In one embodiment, the physical memory sub-system 1402 may take the form of a DRAM circuit.

As shown, the physical memory sub-system 1402 includes a first memory 1404 of a first memory class and a second memory 1406 of a second memory class. In the one embodiment, the first memory class may include non-volatile memory (e.g. FeRAM, MRAM, and PRAM, etc.), and the second memory class may include volatile memory (e.g. SRAM, DRAM, T-RAM, Z-RAM, and TTRAM, etc.). In another embodiment, one of the first memory 1404 or the second memory 1406 may include RAM (e.g. DRAM, SRAM, etc.) and the other one of the first memory 1404 or the second memory 1406 may include NAND flash. In another embodiment, one of the first memory 1404 or the second memory 1406 may include RAM (e.g. DRAM, SRAM, etc.) and the other one of the first memory 1404 or the second memory 1406 may include NOR flash. Of course, in various embodiments, any number of combinations of memory classes may be utilized.

The second memory 1406 is communicatively coupled to the first memory 1404. In one embodiment, the second memory 1406 may be communicatively coupled to the first memory 1404 via direct contact (e.g. a direct connection, etc.) between the two memories. In another embodiment, the second memory 1406 may be communicatively coupled to the first memory 1404 via a bus. In yet another embodiment, the second memory 1406 may be communicatively coupled to the first memory 1404 utilizing a through-silicon via.

As another option, the communicative coupling may include a connection via a buffer device. In one embodiment, the buffer device may be part of the physical memory sub-system 1402. In another embodiment, the buffer device may be separate from the physical memory sub-system 1402.

In one embodiment, the first memory 1404 and the second memory 1406 may be physically separate memories that are communicatively coupled utilizing through-silicon via technology. In another embodiment, the first memory 1404 and the second memory 1406 may be physically separate memories that are communicatively coupled utilizing wire bonds. Of course, any type of coupling may be implemented that functions to allow the second memory 1406 to be communicatively coupled to the first memory 1404.

The physical memory sub-system 1402 is configured to dynamically allocate one or more memory functions from the first memory 1404 of the first memory class to the second memory 1406 of the second memory class. The memory functions may include any number of memory functions and may include any function associated with memory.

For example, in one embodiment, the one or more memory functions may include a cache function. In another embodiment, the memory functions may include a page-related function. A page-related function refers to any function associated with a page of memory. In various embodiments page-related functions may include one or more of the following operations and/or functions (but are not limited to the following): a memory page copy simulating (e.g. replacing, performing, emulating, etc.) for example a software bcopy( ) function; page allocation; page deallocation; page swap; simulated I/O via page flipping (e.g. setting or modifying status or other bits in page tables etc.); etc.

In another embodiment, the memory functions may include a file-related function. A file-related function refers to any function associated with a file of memory. In various embodiments file-related functions may include one or more of the following operations and/or functions (but are not limited to the following): file allocation and deallocation; data deduplication; file compression and decompression; virus scanning; file and filesystem repair; file and application caching; file inspection; watermarking; security operations; defragmentation; RAID and other storage functions; data scrubbing; formatting; partition management; filesystem management; disk quota management; encryption and decryption; ACL parsing, checking, setting, etc; simulated file or buffer I/O via page flipping (e.g. setting or modifying status or other bits in page tables etc.); combinations of these; etc. In yet another embodiment, the memory functions may include a copy operation or a write operation. Still yet, in one embodiment, the memory functions may involve a reclassification of at least one portion of the first memory 1404 of the first memory class.

In one embodiment, the dynamic allocation of the one or more memory functions from the first memory 1404 to the second memory 1406 may be carried out in response to a CPU instruction. For example, in one embodiment, a CPU instruction from a CPU 1410 may be received via a single memory bus 1408. In another embodiment, the dynamic allocation may be carried out independent of at least one aspect of the CPU operation.

As an option, the dynamic allocation of the one or more memory functions may be carried out utilizing logic. In one embodiment, the logic may side on the first memory 1404 and/or the second memory 1406. In another embodiment, the logic may reside on a buffer device separate from the first memory 1404 and the second memory 1406.

Furthermore, in one embodiment, the apparatus 1400 may be configured such that the dynamic allocation of the one or more memory functions includes allocation of the one or more memory functions to the second memory 1406 during a first time period, and allocation of the one or more memory functions back to the first memory 1404 during a second time period. In another embodiment, the apparatus may be configured such that the dynamic allocation of the one or more memory functions includes allocation of the one or more memory functions to the second memory 1406 during a first time period, and allocation of the one or more memory functions to a third memory of a third memory class during a second time period.

More illustrative information will now be set forth regarding various optional architectures and features with which the foregoing techniques discussed in the context of any of the present or previous figure(s) may or may not be implemented, per the desires of the user. For instance, various optional examples and/or options associated with the configuration/operation of the physical memory sub-system 1402, the configuration/operation of the first and second memories 1404 and 1406, the configuration/operation of the memory bus 1408, and/or other optional features have been and will be set forth in the context of a variety of possible embodiments. It should be strongly noted that such information is set forth for illustrative purposes and should not be construed as limiting in any manner. Any of such features may be optionally incorporated with or without the inclusion of other features described.

FIG. 15

FIG. 15 shows a method 1500 for reclassifying a portion of memory, in accordance with one embodiment. As an option, the method 1500 may be implemented in the context of the architecture and environment of the previous Figures, or any subsequent Figure(s). Of course, however, the method 1500 may be implemented in the context of any desired environment. It should also be noted that the aforementioned definitions may apply during the present description.

As shown, a reclassification instruction is received by a physical memory sub-system. See operation 1502. In the context of the present description, a reclassification instruction refers to any instruction capable of being utilized to initiate the reclassification of memory, a portion of memory, or data stored in memory. For example, in various embodiments, the reclassification instruction may include one or more copy instructions, one or more write instructions, and/or any other instruction capable of being utilized to initiate a reclassification.

As shown further, a portion of the physical memory sub-system is identified. See operation 1504. Further, the identified portion of the physical memory sub-system is reclassified, in response to receiving the reclassification instruction, in order to simulate an operation. See operation 1506.

The simulated operation may include any operation associated with memory. For example, in one embodiment, the identified portion of the physical memory sub-system may be reclassified in order to simulate a copy operation. In various embodiments the copy operation may be simulated without necessarily reading the portion of the physical memory sub-system and/or without necessarily writing to another portion of the physical memory sub-system.

Furthermore, various reclassifications may occur in response to the reclassification instruction. For example, in one embodiment, the identified portion of the physical memory sub-system may be reclassified from a page in memory to a file in the memory. In another embodiment, the identified portion of the physical memory sub-system may be reclassified from a file in memory to a page in the memory.

In one embodiment, the identified portion of the physical memory sub-system may be reclassified by editing metadata associated with the identified portion of the physical memory sub-system. The metadata may include any data associated with the identified portion of the physical memory sub-system. For example, in one embodiment, the metadata may include a bit. As an option, the metadata may be stored in a table.

In one embodiment, the identified portion of the physical memory sub-system may be reclassified independent of at least one aspect of a CPU operation. In another embodiment, the identified portion of the physical memory sub-system may be reclassified in response to a CPU instruction. As an option, the CPU instruction may be received via a single memory bus.

For example, in one embodiment, the method 1500 may be implemented utilizing the apparatus 1A-100 or 1400. In this case, the identified portion of the physical memory sub-system may be reclassified utilizing logic residing on the first memory and/or on the second memory. Of course, in another embodiment, the logic may be resident on a buffer device separate from the first memory and the second memory or on any other device.

More illustrative information will now be set forth regarding various optional architectures and features with which the foregoing techniques discussed in the context of any of the present or previous figure(s) may or may not be implemented, per the desires of the user. For instance, various optional examples and/or options associated with the operation 1502, the operation 1504, the operation 1506, and/or other optional features have been and will be set forth in the context of a variety of possible embodiments. It should be strongly noted that such information is set forth for illustrative purposes and should not be construed as limiting in any manner. Any of such features may be optionally incorporated with or without the inclusion of other features described.

FIG. 16

FIG. 16 shows a DIMM using multiple memory classes, in accordance with another embodiment. As an option, the exemplary system of FIG. 16 may be implemented in the context of the architecture and environment of the previous Figure(s), or any subsequent Figure(s). Of course, however, the exemplary system of FIG. 16 may be implemented in the context of any desired environment.

FIG. 16 shows a laptop 1600 and illustrates a computing platform using a dual-in-line memory module (DIMM) 1602 with multiple memory classes as a memory system

In FIG. 16 DIMM 1602 comprises one or more of Component 1604 (e.g. integrated circuit, chip, package, etc.) comprising memory level M1 (e.g. DRAM in one embodiment, etc.); one or more of Component 1606 (e.g. integrated circuit, chip, package, etc.) comprising memory level M2 (e.g. NAND flash in one embodiment if M1 is DRAM, etc.); one or more of Component 1608 (e.g. integrated circuit, chip, package, etc.) comprising memory logic (e.g. buffer chip, etc.).

In different embodiments DIMM 1602 may be an SO-DIMM, UDIMM, RDIMM, etc.

FIG. 17

FIG. 17 shows a computing platform 1700 employing a memory system with multiple memory classes included on a DIMM, and capable of coupling to an Optional Data Disk, in accordance with another embodiment. As an option, the exemplary system of FIG. 17 may be implemented in the context of the architecture and environment of the previous Figure(s), or any subsequent Figure(s). Of course, however, the exemplary system of FIG. 17 may be implemented in the context of any desired environment.

The memory system includes DRAM and NAND flash comprising: a Page File Cache, a PageFile RAM Disk and a Data RAM Disk. Other embodiments may use other configurations of multiple memory classes combined into a single component and coupled to a CPU using a single bus.

FIG. 18

FIG. 18 shows a memory module containing three memory classes, in accordance with another embodiment. As an option, the exemplary system of FIG. 18 may be implemented in the context of the architecture and environment of the previous Figure(s), or any subsequent Figure(s). Of course, however, the exemplary system of FIG. 18 may be implemented in the context of any desired environment.

FIG. 18 illustrates a computing platform using a Memory Module 1802 (e.g. DIMM, SO-DIMM, UDIMM, RDIMM, etc.) with three different memory classes: M1.C1 1804 (e.g. SRAM, etc.), M2.C2 1808 (e.g. DRAM, etc.), and memory class 3 1806 (e.g. NAND flash, etc.). In FIG. 18, Memory Module 1802 also comprises one or more of Component 1810 memory logic (e.g. buffer chip, etc.).

In FIG. 18, memory class 3 1806 is partitioned into six portions (e.g. block, region, part, set, partition, slice, rank, bank, etc.) that include a Page File RAM Disk 1820, a Page File Cache 1822, a Page File Cache RAM Disk 1824, a Data RAM Disk 1826, a Page File Memory 1828, a Data Cache RAM Disk 1830. Different embodiments may use different combination of these portions. Also, in various embodiments, different applications may use different combinations of these portions.

In FIG. 18 Application 1 1832 uses a first portion of memory class 3 1806 portions: a Page File RAM Disk 1820, a Page File Cache 1822, a Page File Cache RAM Disk 1824, a Data RAM Disk 1826. In FIG. 18 Application 3 1834 uses a second, different, portion of memory class 3 1806 portions: a Page File Cache RAM Disk 1824, a Data RAM Disk 1826, a Page File Memory 1828, a Data Cache RAM Disk 1830.

In different embodiments the portions of memory class 3 1806 corresponding to applications (e.g. Application 1 1832, Application 3 1834, etc.) may be separately manipulated (e.g. by the CPU, by the OS, by the Component 1810 memory logic, etc.).

In one embodiment, the portions of memory class 3 1806 corresponding to applications (e.g. Application 1 1832, Application 3 1834, etc.) may correspond to virtual machines (VMs) and the VMs may then easily be swapped in and out of Memory 1812 (e.g. to secondary storage, other device (laptop, desktop, docking station, etc), cloud storage, etc.

In other embodiments, groups of portions (e.g. Application 1 1832, and Application 3 1834 together, etc.) may be manipulated as bundles of memory.

FIG. 19

FIG. 19 shows a system coupled to multiple memory classes using only a single memory bus, and using a buffer chip, in accordance with another embodiment. As an option, the exemplary system of FIG. 19 may be implemented in the context of the architecture and environment of the previous Figure(s), or any subsequent Figure(s). Of course, however, the exemplary system of FIG. 19 may be implemented in the context of any desired environment.

In FIG. 19, System 1900 comprises a CPU 1902 and Memory 1908. In FIG. 19, CPU 1902 is coupled to a buffer chip 1910 (e.g. memory buffer, interface circuit, etc.). In FIG. 19, the CPU 1902 is coupled to Memory 1908 using a Memory Bus 1904. The Memory 1908 comprises a buffer chip 1910 coupled with a component of a memory class 1 1912 and a second component of memory class 2 1914. Note that in such a configuration, a page in a component of memory class 1 could be copied into a component of memory class 2 by the buffer chip 1910 without necessarily using bandwidth of the Memory Bus 1904 or resources of CPU 1902. In one embodiment, some or all of the VMy operations may be performed by the buffer chip 1910 without necessarily using bandwidth of the Memory Bus 1904.

In FIG. 19 Memory Bus 1904 may be of a different width (or may have other different properties, etc.) than the Memory Internal Bus 1906 that couples CPU 1902 to the buffer chip 1910.

FIG. 20

FIG. 20 shows a system 2000 comprising a CPU (in FIG. 20) coupled to a Memory (in FIG. 20) using multiple different memory classes using only a single Memory Bus, and employing a buffer chip (in FIG. 20) with embedded DRAM memory, in accordance with another embodiment. As an option, the exemplary system of FIG. 20 may be implemented in the context of the architecture and environment of the previous Figure(s), or any subsequent Figure(s). Of course, however, the exemplary system of FIG. 20 may be implemented in the context of any desired environment.

In FIG. 20 Bus 2010 and Bus 2008 may have different widths.

In FIG. 20 Bus 2010 may be the same width as Bus 2008 outside the buffer chip but different widths inside the buffer chip.

In FIG. 20 multiple buffer chips may be used so that when they are all connected in parallel the sum of the all the Bus 2010 widths is equal to the Bus 2008 width. Similar alternative embodiments are possible with FIG. 19, 21, 22.

In FIG. 20 memory Class 1 2002 may be SRAM, DRAM, etc.

With the same configuration as FIG. 20 there may be more than one memory class external to the buffer chip.

FIG. 21

FIG. 21 shows a system with a buffer chip (in FIG. 21) and three memory classes on a common bus, in accordance with another embodiment. As an option, the exemplary system of FIG. 21 may be implemented in the context of the architecture and environment of the previous Figure(s), or any subsequent Figure(s). Of course, however, the exemplary system of FIG. 21 may be implemented in the context of any desired environment.

In FIG. 21 System 2100 comprises CPU (in FIG. 21) and Memory (in FIG. 21). Memory uses multiple different memory classes with only a single Memory Bus. CPU is coupled to a buffer chip. buffer chip is coupled to multiple different memory components of different memory classes over a single Internal Memory Bus 2104.

In other embodiments, there may be one or more Internal Memory Bus 2104. That is, not all Memory Classes may be on the same bus in some embodiments.

In one embodiment, memory class 1 (in FIG. 21) and memory class 2 (in FIG. 21) may be on the same bus, and memory class 3 (in FIG. 21) may be on a separate bus.

In another embodiment, memory class 1 and memory class 3 may be on the same bus, and memory class 2 may be on a separate bus.

In some embodiments, there may be connections, communication, coupling etc. (control signals, address bus, data bus) between memory classes. In one embodiment, there may be three possible bi-directional (some may be unidirectional) connections: memory class 1 to memory class 3; memory class 1 to memory class 2; memory class 2 to memory class 3.

FIG. 22

FIG. 22 shows a system with a buffer chip (in FIG. 22) and three memory classes on separate buses, in accordance with another embodiment. As an option, the exemplary system of FIG. 22 may be implemented in the context of the architecture and environment of the previous Figure(s), or any subsequent Figure(s). Of course, however, the exemplary system of FIG. 22 may be implemented in the context of any desired environment.

In FIG. 22 System 2200 comprises CPU 2202 and Memory 2204. Memory uses multiple different memory classes, CPU is coupled to a buffer chip. buffer chip is coupled to multiple different memory components of different memory classes using: Internal Memory Bus 2206; Internal Memory Bus 2208; Internal Memory Bus 2210.

In one embodiment, embedded DRAM (in FIG. 22) (on the buffer chip) may be used for memory class 1 (in FIG. 22). In another embodiment, four or more classes of memory may be utilized.

In some embodiments there may be connections, communication, coupling etc. (control signals, address bus, data bus) between memory classes. There are three possible bi-directional (some may be unidirectional) connections: memory class 1 to memory class 3 (in FIG. 22); memory class 1 to memory class 2 (in FIG. 22); memory class 2 to memory class 3.

FIG. 23A

FIG. 23A shows a system, in accordance with another embodiment. As an option, the exemplary system of FIG. 23A may be implemented in the context of the architecture and environment of the previous Figure(s), or any subsequent Figure(s). Of course, however, the exemplary system of FIG. 23A may be implemented in the context of any desired environment.

FIG. 23A shows a computer platform 2300 that includes a platform chassis 2310, and at least one processing element that consists of or contains one or more boards, including at least one motherboard 2320. Of course, the platform 2300 as shown may comprise a single case and a single power supply and a single motherboard. However, other combinations may be implemented where a single enclosure hosts a plurality of power supplies and a plurality of motherboards or blades.

In one embodiment, the motherboard 2320 may be organized into several partitions, including one or more processor sections 2326 consisting of one or more processors 2325 and one or more memory controllers 2324, and one or more memory sections 2328. In one embodiment, the notion of any of the aforementioned sections is purely a logical partitioning, and the physical devices corresponding to any logical function or group of logical functions might be implemented fully within a single logical boundary, or one or more physical devices for implementing a particular logical function might span one or more logical partitions. For example, the function of the memory controller 2324 may be implemented in one or more of the physical devices associated with the processor section 2326, or it may be implemented in one or more of the physical devices associated with the memory section 2328.

FIG. 23B

FIG. 23B shows a computer system with three DIMMs, in accordance with another embodiment. As an option, the exemplary system of FIG. 23B may be implemented in the context of the architecture and environment of the previous Figure(s), or any subsequent Figure(s). Of course, however, the exemplary system of FIG. 23B may be implemented in the context of any desired environment.

FIG. 23B illustrates an embodiment of a memory system, such as, for example, the Memory System 2358, in communication with a Processor System 2356. In FIG. 23B, one or more Memory Modules 2330 (1)-2330 (N) each contain one or more Flash Chips 2340(1)-2340 (N), one or more buffer chips 2350(1)-2350(N), and one or more DRAMs 2342(1)-2342(N) positioned on (or within) a Memory Module 2330(1).

Although the memory may be labeled variously in FIG. 23B and other figures (e.g. memory, memory components, DRAM, etc), the memory may take any form including, but not limited to, DRAM, synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, etc.), graphics double data rate synchronous DRAM (GDDR SDRAM, GDDR2 SDRAM, GDDR3 SDRAM, etc.), quad data rate DRAM (QDR DRAM), RAMBUS XDR DRAM (XDR DRAM), fast page mode DRAM (FPM DRAM), video DRAM (VDRAM), extended data out DRAM (EDO DRAM), burst EDO RAM (BEDO DRAM), multibank DRAM (MDRAM), synchronous graphics RAM (SGRAM), phase-change memory (PCM), flash memory, and/or any other class of volatile or non-volatile memory either separately or in combination.

FIG. 23C-23F

FIGS. 23C-23F show exemplary systems, in accordance with various embodiments. Alternative embodiments to FIG. 23A, FIG. 23B, and other similar embodiments are possible, including: (1) positioning (e.g. functionally, logically, physically, electrically, etc.) one or more buffer chips 2362 between a Processor System 2364 and Memory 2330 (see, for example, System 2360 in FIG. 23C); (2) implementing the function of (or integrating, packaging, etc.) the one or more buffer chips 2372 within the Memory Controller 2376 of CPU 2374 (see, for example, System 2370 in FIG. 23D); (3) positioning (e.g. functionally, logically, physically, electrically, etc.) one or more buffer chips 2384 (1)-2384 (N) in a one-to-one relationship with memory class 1 2386 (1)-2386 (N) and memory class 2 2388 (1)-2388 (N) in Memory 2382 (see, for example, System 2380 in FIG. 23E); (4) implementing (or integrating the function of, etc.) the one or more buffer chips 2392 within a CPU 2394 (e.g. processor, CPU core, etc.) (see, for example, System 2390 in FIG. 23F).

As an option, the exemplary systems of FIGS. 23C-23F may be implemented in the context of the architecture and environment of the previous Figure(s), or any subsequent Figure(s). Of course, however, the exemplary system of FIGS. 23C-23F may be implemented in the context of any desired environment.

It should be noted that in various embodiments other possible placements of buffer chips 2372 are possible (e.g. on motherboard, on DIMM, on CPU, packaged with CPU, packaged with DRAM or other memory, etc.).

FIG. 24A

FIG. 24A shows a system 2400 using a Memory Bus comprising an Address Bus (in FIG. 24A), Control Bus (in FIG. 24A), and bidirectional Data Bus (in FIG. 24A), in accordance with one embodiment. As an option, the exemplary system of FIG. 24A may be implemented in the context of the architecture and environment of the previous Figure(s), or any subsequent Figure(s). Of course, however, the exemplary system of FIG. 24A may be implemented in the context of any desired environment.

In one embodiment, additional signals may be added to the Memory Bus. The additional signals may be control, status, error, signaling, etc. signals that are in addition to standard (e.g. JEDEC standard DDR2, DDR23, DDR3, etc.) signals.

In one embodiment, the Control Bus may be bidirectional.

In one embodiment, there may be more than one Address Bus (e.g. for different memory classes, etc.).

In one embodiment, there may be more than one Control Bus (e.g. for different memory classes, etc.)

In one embodiment, there may be more than one Data Bus (e.g. for different memory classes, etc.).

In one embodiment, there may be additional buses and/or signals e.g. for control, status, polling, command, coding, error correction, power, etc.).

FIG. 24B

FIG. 24B shows a timing diagram for a Memory Bus (e.g., as shown in FIG. 24A, etc.), in accordance with one embodiment.

As an option, the exemplary system of FIG. 24B may be implemented in the context of the architecture and environment of the previous Figure(s), or any subsequent Figure(s). Of course, however, the exemplary system of FIG. 24B may be implemented in the context of any desired environment.

In FIG. 24B, a Read Command (in FIG. 24B) is placed on the Memory Bus at time t1. The Read Command may comprise address information on the Address Bus (in FIG. 24B) together with control information on the Control Bus (in FIG. 24B). At time t2 the memory places data (the Data Result (in FIG. 24B)) on the Data Bus (in FIG. 24B). The read latency of the memory is the difference in time, t2−t1.

Note that the timing diagram shown in FIG. 24B may vary in detail depending on the exact memory technology and standard used (if any), but in various embodiments the general relationship between signals and their timing may be similar to that shown in FIG. 24B.

FIG. 25

FIG. 25 shows a system with the PM comprising memory class 1 and memory class 2, in accordance with one embodiment. As an option, the exemplary system of FIG. 25 may be implemented in the context of the architecture and environment of the previous Figure(s), or any subsequent Figure(s). Of course, however, the exemplary system of FIG. 25 may be implemented in the context of any desired environment.

In FIG. 25, a first Memory Bus (in FIG. 25) is used to couple the CPU (in FIG. 25) and the memory system. In FIG. 25, a second Memory Bus is used to couple memory class 1 (in FIG. 25) and memory class 2 (in FIG. 25). The second Memory Bus comprises Address Bus A2 (in FIG. 25), Control Bus C2 (in FIG. 25), and bidirectional Data Bus D2 (in FIG. 25).

Note that FIG. 25 does not show details of the coupling between the Memory Bus, the memory system, memory class 1 and memory class 2. The coupling may include, for example, one or more buffer chips or other circuits that are described in detail below.

In FIG. 25, memory class 1 and memory class 2 are shown containing Page X (in FIG. 25). In one embodiment, memory class 1 may serve as a cache (e.g. temporary store, de-staging mechanism, etc.) memory for memory class 2. In one embodiment, a page may be written first to memory class 1 and then subsequently written to memory class 2. In one embodiment, after a page is copied (e.g. moved, transferred, etc.) from memory class 1 to memory class 2 the page may be kept in memory class 1 or may be removed. In different embodiments the CPU may only be able to read from memory Class 1 or may be able to read from both memory class 1 and memory class 2. In one embodiment, the CPU may request that a page be copied from memory class 2 to memory class 1 before being read from memory class 1, etc. Of course, these embodiments, as well as other similar embodiments, as well as different combinations of these and other similar embodiments may be used.

It should thus be noted that the exemplary system of FIG. 25 may be implemented in the context of the architecture and environment of the previous Figure(s), or any subsequent Figure(s) with or without the use of buffer chips (e.g. interface chips, interface circuits, etc.).

FIG. 26

FIG. 26 shows a timing diagram for read commands, in accordance with one embodiment.

In FIG. 26, a normal (e.g. JEDEC standard, other standard, etc.) read (READ1 (in FIG. 26)) is placed on the Address Bus A1 and Control Bus C1 at time t1. In one embodiment, a normal read command may correspond to a request for data that is present in memory class 1. At time t2, if the requested data is present in memory class 1, the requested data from memory class 1 is placed on Data Bus D1. At time t3 a second read command (READ2 (in FIG. 26)) is placed on Address Bus A1 and Control Bus C1. In one embodiment, this read command requests data that is not present in memory class 1 and may result, for example, in a read command for (e.g. addressed to, etc.) memory class 2 being placed on bus A2 and C2 at time t4 (labeled as a Cache Miss and Delayed Read in FIG. 26). At time t5, the requested data from memory class 2 is placed on bus D2. At time t6, the requested data is placed on bus D1.

In one embodiment, the protocol on Memory Bus may be changed to allow the timing to break (e.g. violate, exceed, non-conform to, deviate from, etc.) a JEDEC standard (e.g. DDR2, DDR3, DDR4, etc.) or other standard etc.

In another embodiment, the Memory Bus may use a JEDEC standard (e.g. DDR2, DDR3, DDR4, etc.) or other standard.

In other embodiments, the operation of the memory system may be changed from a standard (e.g. JEDEC, etc.), examples of which will be described below.

FIG. 27

FIG. 27 shows a computing system with memory system and illustrates the use of a virtual memory address (in FIG. 27) (or virtual address, VA), in accordance with one embodiment. The dispatch queue contains a list of threads (in FIG. 27) (1, 2, . . . , N) running on the CPU (in FIG. 27). The Page Table (in FIG. 27) may be used to translate a VA to a PA. In FIG. 27, Page Miss Logic (in FIG. 27) is used to retrieve Page X (in FIG. 27) from the Page File (in FIG. 27) on a page miss.

In other embodiments, the memory address translation and page table logic corresponding to that shown in FIG. 27 may be more complex (e.g. more detailed, more complicated, more levels of addressing, etc.) than shown in FIG. 27 and may include other features (e.g. multiple CPUs, multiple cores, nested page tables, hierarchical addresses, hierarchical page tables, multiple page tables, some features implemented in hardware, some features implemented in hardware, intermediate caches, multiple modes of addressing, etc.), but the basic principles may remain as shown in FIG. 27.

FIG. 28

FIG. 28 shows a system with the PM comprising memory class 1 (in. FIG. 28) and memory class 2 (in FIG. 28) using a standard memory bus, in accordance with one embodiment. As an option, the exemplary system of FIG. 28 may be implemented in the context of the architecture and environment of the previous Figure(s), or any subsequent Figure(s). Of course, however, the exemplary system of FIG. 28 may be implemented in the context of any desired environment. Thus, for example, in one embodiment additional signals may be added to either memory bus shown in FIG. 28. In some embodiments the Control Bus 28-C1 and/or Control Bus 28-C2 may be bidirectional

In FIG. 28, the standard memory bus comprises: Address Bus 28-A1, Data Bus 28-D1, and Control Bus 28-C1. In FIG. 28 a second memory bus comprises: Address Bus 28-A2, Data Bus 28-D2, and Control Bus 28-C2. In FIG. 28, the Page Miss Logic (in FIG. 28) is used to instruct the Memory Controller (in FIG. 28) that a page miss has occurred. The Memory Controller places a command on the Memory Bus to instruct the PM to copy Page X (in FIG. 28) from memory class 2 to memory class 1.

In one embodiment, the CPU (in FIG. 28) uses multiple threads. In one embodiment, the system uses time between executions of threads to fetch (e.g. command, retrieve, move, transfer, etc.) pages (e.g. Page X), as necessary, from memory class 2.

In one embodiment, the fetching of page(s) may be performed in software using hypervisor(s) and virtual machine(s). In other embodiments, the fetching of pages may be performed in hardware. In other embodiments, the fetching of pages may be performed in hardware and/or software.

In one embodiment, memory class 1 may be faster than memory class 2 e.g. (1) memory class 1=DRAM, memory class 2=NAND flash; (2) memory class 1=SRAM, memory class 2=NAND flash; (3) etc.

FIG. 29

FIG. 29 shows a timing diagram for a system employing a standard memory bus (e.g. DDR2, DDR3, DDR4, etc.), in accordance with one embodiment. As an option, the timing diagram of FIG. 29 may be altered depending on the context of the architecture and environment of systems shown in the previous Figure(s), or any subsequent Figure(s) without altering the function.

In FIG. 29, a normal (e.g. JEDEC standard, etc.) read (READ1 (in FIG. 29)) is placed on the Address Bus A1 and Control Bus C1 at time t1. At time t2 the data from memory class 1 is placed on Data Bus D1. At time t3 a second special [e.g. containing special data (e.g. control, command, status, etc.), non-standard, etc.] read command (READ2 (in FIG. 29)) is placed on bus A1 and C1 as a result of a page miss in the CPU. This special read command READ2 may result in a read command for memory class 2 being placed on bus A2 and C2 at time t4 (labeled Cache Miss in FIG. 29). At time t5 (labeled as Page X copied from memory class 2 to memory Class 1 in FIG. 29), the requested data (copied from memory class 2) is placed on bus D2. At time t6 (labeled as READ3 in FIG. 29), the CPU issues another read command (READ3). This read command is a normal read command and results in the requested data from memory class 1 (e.g. copied from memory class 2, transferred from memory class 2, etc.) being placed on bus D1 at time t7 (labeled as CPU reads Page X from memory class 1 in FIG. 29).

In one embodiment, the CPU and memory hardware may be standard (e.g. unaltered from that which would be used with a memory system comprising a single memory class) and the memory bus may also be standard (e.g. JEDEC standard, etc.).

In other embodiments, the read command READ2 may be a different special command (e.g. write command, etc.). Examples of such embodiments are described below.

In other embodiments, the read command READ2 may be one or more commands (e.g. combinations of one or more standard/special write commands and/or one or more standard/special read commands, etc.). Examples of such embodiments are described below.

FIG. 30

FIG. 30 shows a memory system where the PM comprises a memory buffer (e.g. buffer, buffer chip, etc.) (in FIG. 30), memory class 1 (in FIG. 30) and memory class 2 (in FIG. 30), in accordance with one embodiment.

As an option, the exemplary system of FIG. 30 may be implemented in the context of the architecture and environment of the previous Figure(s), or any subsequent Figure(s). Of course, however, the exemplary system of FIG. 30 may be implemented in the context of any desired environment.

In FIG. 30, the memory bus (30-A1, 30-C1, and 30-D1) may use a standard bus protocol (e.g. DDR2, DDR3, DDR4, etc.). In FIG. 30, the buffer chip may be coupled to memory class 1 and memory class 2 using standard (e.g. JEDEC standard, etc.) buses: (30-A2, 30-C2, 30-D2) and (30-A3, 30-C3, 30-D3).

In other embodiments, bus (30-A1, 30-C1, 30-D1) and/or (30-A2, 30-C2, 30-D2) and/or bus (30-A3, 30-C3, 30-D3) (or components (e.g. parts, signals, etc.) of these buses, e.g. 30-A1, 30-C 1, 30-D1, etc.) may be non-standard buses (e.g. modified standard, proprietary, different timing, etc.).

In other embodiments, the buffer chip may comprise one or more buffer chips connected in series, parallel, series/parallel, etc.

FIG. 31

FIG. 31 shows the design of a DIMM (in FIG. 31) that is constructed using a single memory buffer (e.g. buffer, buffer chip, etc.) (in FIG. 31) with multiple DRAM (in FIG. 31) and NAND flash chips (in FIG. 31), in accordance with one embodiment.

As an option, the exemplary design of FIG. 31 may be implemented in the context of the architecture and environment of the previous Figure(s), or any subsequent Figure(s). Of course, however, the exemplary design of FIG. 31 may be implemented in the context of any desired environment.

In FIG. 31, a first memory class is packaged in individual chips on a first side of the DIMM. In FIG. 31, a second memory class is packaged in individual chips on the second side of the DIMM. In FIG. 31, a memory buffer is packaged in an individual chip on the first side of the DIMM.

In one embodiment the DIMM may be a standard design (e.g. standard JEDEC raw card, etc.). In such an embodiment, the space constraints may dictate the number and placement (e.g. orientation, location, etc.) of the memory packages. In such an embodiment, the space constraints may also dictate the number and placement of the memory buffer(s).

In other embodiments, the one or more memory classes may be packaged together (e.g. stacked, etc.).

In other embodiments, the one or more memory buffer(s) may be packaged together (e.g. stacked, etc.) with the one or more memory classes.

FIG. 32

FIG. 32 shows the design of a DIMM constructed using stacked memory chips (in FIG. 32), in accordance with one embodiment.

As an option, the exemplary design of FIG. 32 may be implemented in the context of the architecture and environment of the previous Figure(s), or any subsequent Figure(s). Of course, however, the exemplary design of FIG. 32 may be implemented in the context of any desired environment.

In one embodiment, one or more memory buffer chips may be placed in (e.g. stacked with, integrated with, etc.) the stacked memory chips of FIG. 32 or may be placed in separate packages (on either or both sides of the DIMM shown in FIG. 32).

FIG. 33

FIG. 33 shows a cross-section of a stacked memory chip 3300, in accordance with one embodiment.

In FIG. 33, the buffer (e.g. buffer chip, memory buffer, etc.) (in FIG. 33), DRAM (in FIG. 33) and flash chip (in FIG. 33) are all mounted in the same package.

In FIG. 33, the chips are wire-bonded (in FIG. 33) to a common substrate (in FIG. 33). In FIG. 33, the DRAM chip is packaged face down while the other chips (the DRAM and NAND flash chips in FIG. 33) may be packaged face up. In some embodiments, packaging a chip face down may allow the bond wires to be short and thus may allow the chip to operate at a higher clock frequency. In other embodiments the chips may be stacked in a different order than that shown in FIG. 33 (e.g. buffer chip at the bottom packaged face down, etc.). In other embodiments, the chips may be stacked (e.g. packaged, arranged, located, situated, etc.) in a different manner than that shown in FIG. 33 (e.g. two smaller chips side by side above/below one or more larger chips, etc.).

In one embodiment, the chips are bonded to a Fine-pitch Ball Grid Array (FBGA) substrate. In other embodiments, the package may be of a different type (e.g. chip-scale package (CSP), ball grid array (BGA), PLCC, PQFP, VQFP, VQFP, QFN, etc.).

In one embodiment, the stacked memory chip may use more than one substrate.

In one embodiment, the stacked memory chip may use more than one package (e.g. package-on-package (PoP) construction, package-in-package construction (PiP), etc.).

In one embodiment, the stacked memory chip may use one or more interposers (e.g. passive layers between chips, etc.).

In one embodiment, the stacked memory chip may use one or more redistribution layers (e.g. RDL, etc.).

In another embodiment, the stacked memory chip may use more than one memory class technology and/or more than one buffer chip (e.g.: (1) 2 NAND flash chips, 1 DRAM chip, 1 buffer chip; (2) 1 NAND flash chip, 2 DRAM chips, 2 buffer chips; etc.)

In other embodiments, the stacked memory chip may use any kind of memory class (e.g. not limited to NAND flash plus DRAM, etc.).

In other embodiments, the stacked memory chip may use more than two memory classes.

FIG. 34A

FIG. 34A shows a logical block diagram for a buffer chip (in FIG. 34A) connected to a standard SDRAM (in FIG. 34A), in accordance with one embodiment.

In FIG. 34A the diagram shows the delays associated with a read command. In FIG. 34A delay d1 is the delay of the address signals through the buffer chip. In FIG. 34A delay d2 is the read latency of the DDRX (e.g. DDR2, DDR3, DDR4, etc.) SDRAM. In FIG. 34A, delay d3 is the delay of the data through the buffer chip.

In one embodiment, the delays d1, d2, d3 may be made integer multiples (or nearly so) of the CPU clock. In such an embodiment bus (34A-A1, 34A-C1, 34A-D1) and/or bus (34A-A1D, 34A-C1D, 34A-D1D) may be a standard bus (e.g. JEDEC standard, etc.). In such an embodiment, bus (34A-A1D, 34A-C1D, 34A-D1D) may adhere to the same standard as bus (34A-A1, 34A-C1, 34A-D1) but use a different timing.

In another embodiment the delays d1, d2, d3 may be made fractional multiples of the CPU clock.

FIG. 34B

FIG. 34B shows a timing diagram corresponding to the system of FIG. 34A, in accordance with one embodiment.

In FIG. 34B, the CPU places a read command on bus A1 and bus C1 at time t1. At time t2 after delay D1, due to the I/O latency of the buffer chip, the read command appears on bus MD and C1D. At time t3 after further delay D2, due to the read latency of the SDRAM, the SDRAM places the requested data on bus D1D. At time t4 after further delay D3 due to the buffer chip the requested data is placed on bus D1.

In one embodiment, the buffer chip may manipulate (e.g. modify, alter, transform, logically alter, etc.) the bus protocol(s) in order to avoid protocol violations (e.g. bus collisions, timing parameter violations, etc.).

FIG. 35

FIG. 35 shows a stacked memory chip 3500, in accordance with one embodiment.

In FIG. 35, the buffer (e.g. buffer chip, memory buffer, etc.) (in FIG. 35), DRAM (in FIG. 35) and flash chip (in FIG. 35) are all mounted in the same package using wire-bonding (in FIG. 35).

In FIG. 35, the chips are wire-bonded to a common substrate (in FIG. 35). In FIG. 35, all chips may be packaged face up. In some embodiments, packaging a chip face down may allow the bond wires to be short and thus allow the chip to operate at a higher clock frequency. In other embodiments, the chips may be stacked in a different order than that shown in FIG. 35 (e.g. buffer chip at the bottom, etc.). In other embodiments, the chips may be stacked (e.g. packaged, arranged, located, situated, etc.) in a different manner than that shown in FIG. 35 (e.g. two small chips side by side above/below one or more larger chips, etc.).

In one embodiment, the chips may be bonded to a Fine-pitch Ball Grid Array (FBGA) substrate. In other embodiments, the package may be of a different type (e.g. chip-scale package (CSP), ball grid array (BGA), PLCC, PQFP, VQFP, VQFP, QFN, etc.).

In one embodiment, the stacked memory chip may use more than one substrate.

In one embodiment, the stacked memory chip may use more than one package (e.g. package-on-package (PoP) construction, package-in-package construction (PiP), etc.).

In one embodiment, the stacked memory chip may use one or more interposers (e.g. passive layers between chips, etc.).

In one embodiment, the stacked memory chip may use one or more redistribution layers (e.g. RDL, etc.).

In another embodiment, the stacked memory chip may use more than one memory class technology and/or more than one buffer chip (e.g.: (1) 2 NAND flash chips, 1 flash chip, 1 buffer chip; (2) 1 NAND flash chip, 2 DRAM chips, 2 buffer chips; etc.)

In other embodiments, the stacked memory chip may use any kind of memory class (e.g. not limited to NAND flash plus DRAM, etc.).

In other embodiments, the stacked memory chip may use more than two memory classes.

FIG. 36

FIG. 36 shows a stacked memory chip 3600 using through-silicon vias (TSV) (In FIG. 36), in accordance with one embodiment.

In FIG. 36, the buffer (e.g. buffer chip, memory buffer, etc.) (in FIG. 36), DRAM chips (in FIG. 36), and flash chips (in FIG. 36) are all mounted in the same package using TSV.

In FIG. 36, in one embodiment, the buffer chip is placed at the bottom of the stack and wire-bonded (in FIG. 36) to a substrate (in FIG. 36). In FIG. 36, the buffer chip is packaged face down which may allow the bond wires to be short and thus allow the chip to operate at a higher clock frequency. In other embodiments, the chips may be stacked in a different order than that shown in FIG. 36 (e.g. buffer chip at the top, etc.). In other embodiments, the chips may be stacked (e.g. packaged, arranged, located, situated, etc.) in a different manner than that shown in FIG. 36 (e.g. two small chips side by side above/below one or more larger chips, etc.).

In one embodiment, the chips are bonded to a Fine-pitch Ball Grid Array (FBGA) substrate. In other embodiments, the package may be of a different type [e.g. chip-scale package (CSP), ball grid array (BGA), PLCC, PQFP, VQFP, VQFP, QFN, combinations of these, etc.].

In one embodiment, the stacked memory chip may use more than one substrate.

In one embodiment, the stacked memory chip may use more than one package (e.g. package-on-package (PoP) construction, package-in-package construction (PiP), combinations of packages, etc.).

In one embodiment, the stacked memory chip may use one or more interposers (in FIG. 36) (e.g. passive layers between chips, etc.), as shown in FIG. 36.

In one embodiment, the stacked memory chip may use one or more redistribution layers (e.g. RDL, etc.), not shown in FIG. 36.

In another embodiment, the stacked memory chip may use different numbers of each memory class and/or more than one buffer chip (e.g.: (1) 2 NAND flash chips, 1 DRAM chip, 1 buffer chip; (2) 1 NAND flash chip, 2 DRAM chips, 2 buffer chips; etc.)

In other embodiments, the stacked memory chip may use any kind of memory class (e.g. not limited to NAND flash plus DRAM, etc.).

In other embodiments, the stacked memory chip may use more than two memory classes.

FIG. 37A

FIG. 37A shows a method to address memory using a Page Table (in FIG. 37A), in accordance with one embodiment.

In FIG. 37A, the Page Table contains the mappings from VA to PA. As shown in FIG. 37A, VA=00 maps to PA=01 and Page 01 in the Page Table. As shown in FIG. 37A, PA=01 and Page 01 contains data 0010_(—)1010 in the DRAM (in FIG. 37A). As shown in FIG. 37A, the Page Table is 8 bits in total size, has 4 entries, each entry being 2 bits. As shown in FIG. 37A, the DRAM is 32 bits in size. As shown in FIG. 37A, the VA is 2 bits and the PA is 2 bits.

In one embodiment of a CPU architecture, the PA and VA may be different than that shown in FIG. 37A (e.g. 32 bits, 64 bits, different lengths, etc.). In a one embodiment of a memory system architecture, the DRAM may be different (e.g. much larger) than that shown in FIG. 37A (e.g. 1 GB-256 GB, 8 Gbit-2Tbit, etc.). In one embodiment of a CPU architecture, the page table(s) (and surrounding logic, etc.) may be more complex than that shown in FIG. 37A [e.g. larger, nested, multi-level, combination of hardware/software, including caches, multiple tables, multiple modes of use, hierarchical, additional (e.g. status, dirty, modified, protection, process, etc.) bits, etc.] and may be a page table system rather than a simple page table.

In some embodiments, the page table system(s) may maintain a frame table and a page table. A frame, sometimes called a physical frame or a page frame, is a continuous region of physical memory. Like pages, frames are be page-size and page-aligned. The frame table holds information about which frames are mapped. In some embodiments, the frame table may also hold information about which address space a page belongs to, statistics information, or other background information.

The page table holds the mapping between a virtual address of a page and the address of a physical frame. In some embodiments, auxiliary information may also be kept (e.g. in the page table, etc.) about a page such as a present bit, a dirty bit, address space or process ID information, amongst others (e.g. status, process, protection, etc.).

In some system embodiments, secondary storage (e.g. disk, SSD, NAND flash, etc.) may be used to augment PM. Pages may be swapped in and out of PM and secondary storage. In some embodiments, a present bit may indicate the pages that are currently present in PM or are on secondary storage (the swap file), and may indicate how to access the pages (e.g. whether to load a page from secondary storage, whether to swap another page in PM out, etc.).

In some system embodiments, a dirty bit (or modified bit) may allow for performance optimization. A page on secondary storage that is swapped in to PM, then read, and subsequently paged out again does not need to be written back to secondary storage, since the page has not changed. In this case the dirty bit is not set. If the page was written to, the dirty bit is set. In some embodiments the swap file retains a copy of the page after it is swapped in to PM (thus the page swap operation is a copy operation). When a dirty bit is not used, the swap file need only be as large as the instantaneous total size of all swapped-out pages at any moment. When a dirty bit is used, at all times some pages may exist in both physical memory and the swap file.

In some system embodiments, address space information (e.g. process ID, etc.) is kept so the virtual memory management (VMM) system may associate a pages to a process. In the case, for example, that two processes use the same VA, the page table contains different mappings for each process. In some system embodiments, processes are assigned unique IDs (e.g. address map identifiers, address space identifiers, process identifiers (PIDs), etc.). In some system embodiments, the association of PIDs with pages may be used in the selection algorithm for pages to swap out (e.g. candidate pages, etc.). For example, pages associated with inactive processes may be candidate pages because these pages are less likely to be needed immediately than pages associated with active processes.

In some system embodiments, there may be a page table for each process that may occupy a different virtual-memory page for each process. In such embodiments, the process page table may be swapped out whenever the process is no longer resident in memory.

Thus it may be seen that, as an option, the exemplary design of FIG. 37A may be implemented in the context of the architecture and environment of the previous Figure(s), or any subsequent Figure(s). Of course, however, the exemplary design of FIG. 37A may be implemented in the context of any desired environment.

FIG. 37B

FIG. 37B shows a method to map memory using a window, in accordance with one embodiment.

In FIG. 37B there are two memory classes: (1) memory class 1, DRAM (in FIG. 37B); (2) memory class 2, NAND flash (in FIG. 37B). In a system corresponding to the diagram of FIG. 37B that contains more than one memory class it is possible that there are insufficient resources (e.g. address space is too small, address bus is too small, software and/or hardware limitations, etc.) to allow the CPU to address all of the memory in the system.

In one embodiment, the method of FIG. 37B may have two distinct characteristics: (1) the memory class 2 address space (e.g. NAND flash size, etc.) may be greater than the address space of the memory bus; (2) data is copied from NAND flash to DRAM before it may be read by the CPU.

In FIG. 37B, a first memory class (e.g. DRAM, etc.) may be used as a movable (e.g. controllable, adjustable, etc.) window into a (larger) second memory class (e.g. NAND flash, etc.). The address space of the window is small enough that it may be addressed by the CPU. The window may be controlled (e.g. moved through the larger address space of the second memory class, etc.) using the page table in the CPU.

FIG. 37B has been greatly simplified to illustrate the method. In FIG. 37B, the Page Table (in FIG. 37B) contains the mappings from VA to PA. As shown in FIG. 37B the Page Table has 16 entries (000−111), each entry being 2 bits. As shown in FIG. 37A, the DRAM is 4 pages, or 32 bits in size. As shown in FIG. 37A, the NAND flash is 8 pages, or 64 bits in size. As shown in FIG. 37A, the VA is 2 bits and the PA is 2 bits. There are 2 bits of PA (corresponding to 4 addresses) so all 8 pages in NAND flash cannot be directly addressed by the CPU. As shown in FIG. 37B, VA=010 initially (indicated by the dotted arrow marked 1) maps to PA=01 and Page 01 in the Page Table. As shown in FIG. 37B, PA=01 and Page 01 contains data 0011_(—)0101 in the DRAM. This data 0011_(—)0101 was previously copied from the NAND flash, as shown (indicated by the dotted arrow marked 2) in FIG. 37B. At a later time the CPU uses VA=000 to access data that is not in DRAM (indicated by the solid arrow marked 3). As shown in FIG. 37B, VA=110 now maps to PA=01 and Page 01 in the Page Table. The old mapping at VA=000 in the Page Table is invalidated (e.g. removed, deleted, marked by using a bit in the page table, etc.). A copy operation is used to move the requested data 0010_(—)1010 from NAND flash to DRAM (indicated by the solid arrow marked 4). The CPU is now able to read data 0010_(—)1010 from the DRAM.

Thus in order to obtain data at VA (e.g. data corresponding to VA=110) the following steps are performed: (1) a page in DRAM is selected (e.g. Page=01) that may be used (e.g. replaced, ejected, etc.); (2) the data (e.g. 0010_(—)1010 at address corresponding to VA=110) is copied from NAND flash to DRAM (e.g. Page=01 in DRAM); (3) the Page Table is updated (e.g. so that VA=110 maps to Page=01); (4) the old Page Table entry (e.g. VA=000) is invalidated; (5) the CPU performs a read to VA (e.g. VA=110); (6) the Page Table maps VA to PA (e.g. from VA=110 to PA=01 and Page=01 in the DRAM); (6) the data is read from PA (e.g. 0010_(—)1010 from DRAM).

In FIG. 37B, the DRAM forms a 32-bit window into the 64-bit NAND flash. In one embodiment, the 32-bit window is divided into 4 sets. Each set may hold a word of 8 bits. Each set may hold one word from the NAND flash. In one embodiment a table (e.g. TLB) in hardware in the CPU or software (e.g. in the OS, in a hypervisor, etc.) keeps the mapping from VA to PA as a list of VAs. In one embodiment, the list of VAs may be a rolling list. For example, 8 VAs may map to 4 PAs, as in FIG. 37B. In such an embodiment, as PAs in the DRAM are used up a new map is added and the old one invalidated, thus forming the rolling list. Once all 8 spaces have been used, the list is emptied (e.g. TLB flushed, etc.) and the list started again.

In one embodiment (A), the CPU and/or OS and/or software (e.g. hypervisor, etc.) may keep track of which pages are in DRAM. In such an embodiment (A), a hypervisor may perform the VA to PA translation, determine the location of the PA, and may issue a command to copy pages from NAND flash to DRAM if needed.

In another embodiment (B), a region of NAND flash may be copied to DRAM. For example, in FIG. 37B, if an access is required to data that is in the upper 32 bits of the 64-bit NAND flash, a region of 32 bits may be copied from NAND flash to the 32-bit DRAM.

In other embodiments, combinations of embodiment (A) and embodiment (B), as just described, may be used.

In a one embodiment of a CPU architecture, the PA and VA may be different than that shown in FIG. 37B (e.g. 32 bits, 64 bits, different lengths, etc.). In a one embodiment of a memory system architecture, the DRAM may be different (e.g. much larger) than that shown in FIG. 37B (e.g. 1 GB-256 GB, 8 Gbit-2Tbit, etc.). In a one embodiment of a CPU architecture, the page table(s) (and surrounding logic, etc.) may be more complex than that shown in FIG. 37B.

Thus, for example, in embodiments using multiple memory classes together with an existing CPU and/or OS architecture, the architecture may be more complex than that shown in FIG. 37B both in order to accommodate the existing architecture and because the architecture is inherently more complex than that shown in FIG. 37B.

In other embodiments, the page table(s) may be more complex than shown in FIG. 37B (e.g. larger, nested, multi-level, combination of hardware/software, include caches, use table lookaside buffer(s) (e.g. TLB, etc.), use multiple tables, have multiple modes of use, be hierarchical, use additional (e.g. status, dirty, modified, protection, process, etc.) bits, or use combinations of any these, etc.). In some embodiments, the page table may be a page table system (e.g. multiple tables, nested tables, combinations of tables, etc.) rather than a simple page table.

In FIG. 37B, for the purposes of addressing the DRAM may also be viewed as a cache for the NAND flash. As such any addressing and caching scheme may be used in various alternative embodiments. For example, in some embodiments, the addressing scheme may use tags, sets, and offsets. In some embodiments, the address mapping scheme may use direct mapping, associative mapping, n-way set associative mapping, etc. In some embodiments, the write policy for the memory classes may be write back, write through, etc.

Thus it may be seen that, as an option, the exemplary design of FIG. 37B may be implemented in the context of the architecture and environment of the previous Figure(s), or any subsequent Figure(s). Of course, however, the exemplary design of FIG. 3B may be implemented in the context of any desired environment.

In some embodiments memory class 1 may be SRAM, memory class 2 may be DRAM, etc. In some embodiments memory may be of any technology (e.g. SDRAM, DDR, DDR2, DDR3, DDR4, GDDR, PRAM, MRAM, FeRAM, embedded DRAM, eDRAM, SRAM, etc.).

FIG. 38

FIG. 38 shows a flow diagram that illustrates a method to access PM that comprises two classes of memory, in accordance with one embodiment.

In other embodiments: (1) Step 2 may be performed by the CPU, by software (e.g. hypervisor, etc.) or by the memory system; (2) Step 4 may be a READ command that may trigger the memory system to copy from memory class 2 (MC2) to memory class 1 (MC1) if required; (3) Step 4 may be a WRITE command to a special location in PM that may trigger the memory system to copy from memory class 2 (MC2) to memory class 1 (MC1) if required; (4) Step 6 may be a retry mechanism (either part of a standard e.g. JEDEC, etc. or non-standard); (5) Step 4 may be a READ command to which the PM may respond (e.g. with a special code, status, retry, etc.); (6) Step 6 may be a poll (e.g. continuous, periodic, repeating, etc.) from the CPU to determine if data has been copied to MC1 and is ready; (7) the PM may respond in various ways in step 7 (e.g. retry, special data with status, expected time to complete, etc.).

FIG. 39

FIG. 39 shows a system to manage PM using a hypervisor, in accordance with one embodiment.

In FIG. 39, the Hypervisor (in FIG. 39) may be a software module and may allow the CPU (in FIG. 39) to run multiple VMs. In FIG. 39, the Hypervisor contains two VMs, VM1 (in FIG. 39) and VM2 (in FIG. 39). In FIG. 39 VM2 may make a request for VA1. The Address Translation (in FIG. 39) block in the Hypervisor translates this address to VA2. Using a custom address translation block may allow the Hypervisor to determine if VA2 is held in memory class 1 (MC1) (in FIG. 39) or in memory class 2 (MC2) (in FIG. 39). If the data is held in MC2 then one of the mechanisms or methods already described may be used to copy (or transfer, move, etc.) the requested data from MC2 to MC1.

In some embodiments, the Address Translation block may be in hardware. In other embodiments, the Address Translation block may be in software. In some embodiments, the Address Translation block may be a combination of hardware and software.

FIG. 40

FIG. 40 shows details of copy methods in a memory system that comprises multiple memory classes, in accordance with one embodiment.

As an option, the exemplary methods of FIG. 40 may be implemented in the context (e.g. in combination with, as part of, together with, etc.) of the architecture and environment of the previous Figure(s), or any subsequent Figure(s).

In a memory system with multiple memory classes, copies between two (or more) memory classes may be performed using several methods (or combinations of methods, etc.).

A first method is shown in FIG. 40 and uses two steps: Copy 1 and Copy 2. In this method Copy 1 copies Page X (1) (in FIG. 40) from memory class 1 (in FIG. 40) to Page X (2) (in FIG. 40) in the CPU (in FIG. 40) using the Memory Bus (in FIG. 40). In one embodiment, the CPU may perform Copy 1. Other methods of performing Copy 1 include, but are not limited to: (1) use of direct cache injection; (2) use of a DMA engine; (3) other hardware or software copy methods; (4) combinations of the above. Copy 2 then copies Page X (2) to Page X (3) (in FIG. 40) using the Memory Bus. The CPU may also perform Copy 2, although other methods of performing Copy 2 are possible. Copy 1 and Copy 2 do not have to use the same methods, but they may.

A second method in FIG. 40 uses a single step (Copy 3) and does not necessarily require the use of the Memory Bus. In one embodiment, the Memory Bus may be a high-bandwidth and constrained resource. In some embodiments, use of the Memory Bus for CPU traffic may be maximized while use for other purposes may be minimized. For example, some embodiments may avoid using the Memory Bus for copies between memory classes.

In FIG. 40 the step labeled Copy 3 copies Page X (1) in memory class 1 directly to Page X (3) in memory class 2 (in FIG. 40). The step Copy 3 may be initiated by the CPU using a command over the Memory Bus. The step Copy 3 may also be initiated by a memory controller (not shown in FIG. 40) in the memory system. The memory controller or memory controllers may be located anywhere in the system as shown in several previous embodiments: (1) e.g. in a buffer chip located on a DIMM, motherboard, etc; (2) embedded on one or more of the chips, packages etc. that contain one or more of the memory classes shown in FIG. 40; (3) part of the CPU; (4) a combination of the above.

In FIG. 40, one or more triggers (e.g. commands, signals, etc.) for the memory controller to initiate a copy may include: (1) wear-leveling of one of the memory classes; (2) maintenance of free space in one of the memory classes; (3) keeping redundant copies in multiple memory classes for reliability; (4) de-staging of cached data from one memory class to another; (5) retrieval of data on a CPU command; (5) other triggers internal to the memory system; (6) other external triggers e.g. from the CPU, OS, etc; (7) other external triggers from other system components or software; (8) combinations of any of the above.

In FIG. 40, during the step Copy 3 in some embodiments the memory controller may also perform an operation on the Memory Bus during some or all of the period of step Copy 3. In one embodiment, the following sequence of steps may be performed, for example: (1) disconnect the Memory Bus from the CPU; (2) raise a busy flag (e.g. assert a control signal, set a status bit, etc.); (3) issue a command to the CPU; (4) alter the normal response, protocol, or other behavior; (5) any combination of the above.

In FIG. 40, in some embodiments, the memory controller may also interact with the CPU before, during, or after the step Copy 3 using a control signal (e.g. sideband signal, etc.) separate from the main Memory Bus or part of the Memory Bus. The control signal (not shown in FIG. 40) may use: (1) a separate wire; (2) separate channel; (3) multiplexed signal on the Memory Bus; (4) alternate signaling scheme; (5) a combination of these, etc.

In some embodiments, one copy method may be preferred over another. For example, in a system where performance is important an embodiment may use a single copy that avoids using the Memory Bus. In a system where power is important an embodiment may use a slow copy using the Memory Bus that may use less energy.

The choice of embodiments and copy method(s) may depend on the relative power consumption of the copy method(s) and other factors. It is also possible, for example, that a single copy without the use of the Memory Bus consumes less power than a copy that does require the use of the Memory Bus. Such factors may change with time, user and/or system preferences, or other factors etc. For example, in various embodiments, the choice of copy method(s) may depend on: (1) whether the system is in “sleep”, power down, or other special power-saving mode (e.g. system failure, battery low, etc.) or other performance mode etc; (2) the length (e.g. file size, number of pages, etc.), type (e.g. contiguous, sequential, random, etc.), etc. of the copy; (3) any special requirements from the user, CPU, OS, system, etc. (e.g. low latency required for real-time transactions (e.g. embedded system, machine control, business, stock trading, etc.), games, audio, video or other multi-media content, etc.). In some embodiments, the system may modify (e.g. switch, select, choose, change, etc.) the copy method either under user and/or system control in a manual and/or automatic fashion. In some embodiments, the system may modify copy methods during a copy.

FIG. 41

FIG. 41 shows a memory system architecture comprising multiple memory classes and a buffer chip with memory, in accordance with one embodiment. As an option, the exemplary architecture of FIG. 41 may be implemented in the context (e.g. in combination with, as part of, together with, etc.) of the architecture and environment of the previous Figure(s), or any subsequent Figure(s).

As shown in FIG. 41, the buffer chip (in FIG. 41) may be connected between the CPU (in FIG. 41) and multiple memory classes. In FIG. 41, the buffer chip is shown connected to memory class 2 (in FIG. 41) using Bus 2 (in FIG. 41) and connected to memory class 3 (in FIG. 41) using Bus 3 (in FIG. 41).

In one embodiment, memory class 1 (in FIG. 41) may be used as a cache for the rest of the memory system (comprising memory class 2 and memory class 3). In such an embodiment the PA from the CPU etc. may be divided into tag, block and offset to determine if requested data is present in the cache. In various embodiments, the type of cache mapping (e.g. direct mapping, fully associative, k-way associative, etc.) and the cache policy (e.g., write back, write through, etc.) may be implemented in any desired manner.

Other embodiments may include (but are not limited to) the following variations: (1) more than two memory classes may be connected to the buffer chip; (2) less than two memory classes may be connected to the buffer chip (3); the memory classes may be any memory technology (e.g. DRAM, NAND flash, etc); (4) Bus 2 and Bus 3 may be combined or separate as shown; (5) alternative bus arrangements may be used: e.g. a common bus, multi-drop bus, multiplexed bus, bus matrix, switched bus, split-transaction bus, PCI bus, PCI Express bus, HyperTransport bus, front-side bus (FSB), DDR2/DDR3/DDR4 bus, LPDDR bus, etc; (6) memory class 2 and memory class 3 may be combined on the same chip or in the same package; (7) memory class 2 may be embedded, contained or part of memory class 3; (8) memory class 1 may be located in a different part of the system physically while still logically connected to the buffer chip; (9) any combination of the above. In FIG. 41, the buffer chip is shown as containing memory class 1. memory class 1 may be a special class of memory e.g. fast memory, such as SRAM or embedded DRAM for example, used as a cache, scratchpad or other working memory etc. that the buffer chip may use to hold data that needs to be fetched quickly by the CPU for example. Other examples of use for memory class 1 (or any of the other memory classes separately or in combination with memory class 1) may include: (1) test, repair, re-mapping, look-aside etc. tables listing, for example, bad memory locations in one or more of the memory classes; (2) page tables; (3) other memory address mapping functions; (4) cache memory holding data that later be de-staged to one or more of the other memory classes; (5) timing parameters used by the system and CPU; (6) code and data that may be used by the buffer chip; (7) power management (e.g. the buffer chip, OS, CPU etc. may turn off other parts of the system while using memory class 1 to keep energy use low etc.); (8) log files for memory-mapped storage in one or more of the memory classes; (9) combinations of the above.

FIG. 42

FIG. 42 shows a memory system architecture comprising multiple memory classes and multiple buffer chips, in accordance with one embodiment. As an option, the exemplary architecture of FIG. 42 may be implemented in the context (e.g. in combination with, as part of, together with, etc.) of the architecture and environment of the previous Figure(s), or any subsequent Figure(s).

In FIG. 42, buffer chip 1 (in FIG. 42) interfaces the CPU (in FIG. 42) and memory class 1 (in FIG. 42) and buffer chip 2 (in FIG. 42) interfaces memory class 1 and memory class 2 (in FIG. 42). For example in one embodiment, Bus 1 (in FIG. 42) may be a standard memory bus such as DDR4. memory class 1 may be a fast memory such as SRAM. In such an embodiment Bus 2 (in FIG. 42) may be different (e.g. use a different protocol, timing etc.) than Bus 1. In FIG. 42, buffer chip 1 may perform a conversion of timing, protocol etc. In FIG. 42, memory class 1 is shown as separate from buffer chip 1 and memory class 1.

In alternative embodiments, memory class 1 may be: (1) part of buffer chip 1; (2) part of buffer chip 2; (3) embedded with one or more other parts of the system; (4) packaged with one or more other parts of the system (e.g. in the same integrated circuit package).

In FIG. 42, memory class 1 is shown as using more than one bus e.g. Bus 2 and Bus 3 (in FIG. 42). In one embodiment, memory class 1 is an embedded DRAM or SRAM that is part of one or more of the buffer chips. In alternative embodiments, memory class 1 may not use a shared bus.

In other embodiments: (1) memory class 1 may use a single bus shared between buffer chip 1 and buffer chip 2 for example; (2) buffer chip 1 and buffer chip 2 may be combined and share a single bus to interface to memory class 1; (3) buffer chip 2 may interface directly to buffer chip 1 instead of (or in addition to) memory Class 1; (4) any combinations of the above.

In one embodiment, memory class 1 may be a fast, small memory (such as SRAM, embedded DRAM, SDRAM, etc.) and able to quickly satisfy requests from the CPU. In such an embodiment, memory class 2 may be a larger and cheaper but slower memory (such as NAND flash, SDRAM, etc.).

The various optional features of the architectures based on that shown in FIG. 42 (and other similar architectures presented in other Figure(s) here) include (but are not limited to): (1) low power (e.g. using the ability to shut down memory class 2 in low-power modes, etc.); (2) systems design flexibility (e.g. while still using an existing standard memory bus for Bus 1 with new technology for remaining parts of the system, or using a new standard for Bus 1 and/or other system components while using existing standards for the rest of the system, etc.); (3) low cost (e.g. mixing high performance but high cost memory class 1 with lower performance but lower cost memory class 2, etc.); (4) upgrade capability, flexibility with (planned or unplanned) obsolescence (e.g. using an old/new CPU with new/old memory, otherwise incompatible memory and CPU, etc.); (5) combinations of the above.

In alternative embodiments, Bus 1 and Bus 2 (or any combination Bus X and Bus Y of the bus connections shown in FIG. 42, such as Bus 3 and Bus 4 (in FIG. 42), Bus 2 and Bus 3, or other combinations of 2, 3, or 4 buses etc.) may use: (1) the same protocol; (2) the same protocol but different timing versions (e.g. DDR2, DDR3, DDR4 but with a different timing, etc.); (3) different data widths (e.g. Bus X may use 64 bits of data and Bus Y may use 512 bits etc.); (4) different physical versions of the same protocol (e.g. Bus X may be a JEDEC standard DDR3 bus with a 72-bit wide bus with ECC protection intended for registered DIMMs; Bus Y may be the same JEDEC standard DDR3 bus but with a 64-bit wide data bus with no ECC protection intended for unbuffered DIMMs, etc.); (5) other logical or physical differences such as type (multi-drop, multiplexed, parallel, split transaction, packet-based, PCI, PCI Express, etc.); (6) combinations of the above.

FIG. 43

FIG. 43 shows a memory system architecture comprising multiple memory classes and an embedded buffer chip, in accordance with one embodiment. As an option, the exemplary architecture of FIG. 41 may be implemented in the context (e.g. in combination with, as part of, together with, etc.) of the architecture and environment of the previous Figure(s), or any subsequent Figure(s).

In FIG. 43, the buffer chip (in FIG. 43) is shown as embedded in memory class 1 (in FIG. 43). In alternative embodiments: (1) the buffer chip (or multiple buffer chips) may be packaged with one or more chips, die, etc. comprising one or more components of memory class 1; (2) one or more buffer chips may be connected to one or more of memory class 1 chips, die, components etc. using through-silicon vias (TSV) or other advanced high-density interconnect (HDI) techniques (e.g. chip on board, stacked, wire-bond, etc.); (3) combinations of the above.

In FIG. 43, Bus 1 (in FIG. 43), the memory bus, is shown as connected to memory class 1, but in various embodiments may be connected to the buffer chip, or may be connected to both the buffer chip and memory class 1. In FIG. 43, Bus 2 (in FIG. 43) is shown as connecting the buffer chip and memory Class 2 (in FIG. 43), but in various embodiments may connect memory class 2 to memory class 1 or may connect memory class 2 to both memory Class 1 and the buffer chip. In other embodiments there may be more than two memory classes or a single memory class (omitting memory class 1 or memory class 2).

Some embodiments may emulate the appearance that only a single memory class is present. For example, in one embodiment there may be system modes that require certain features (e.g. low-power operation, etc.) and such an embodiment may modify Bus 2 (e.g. disconnect, shut off, power-down, modify mode, modify behavior, modify speed, modify protocol, modify bus width, etc.) and memory class 2 (shut-off, change mode, power-down, etc.). In other embodiments memory class 2 may be remote or appear to be remote (e.g. Bus 2 may be wireless, memory class 2 may be in a different system, Bus 2 may involve a storage protocol, Bus 2 may be WAN, etc.).

In some embodiments, the system configuration (e.g. number and type of buses, number and technology of memory classes, logical connections, etc.) may, for example, be functionally changed from a two-class memory system to a conventional single-class memory system.

In some embodiments, based on FIG. 43, in which there may be more than two memory classes for example, the system configuration may be changed from n-class to m-class (e.g. from 3 memory classes to 1, 3 classes to 2, 2 classes to 3, etc.) depending on different factors (e.g. power, speed, performance, etc.). Such factors may vary with time and in some embodiments changes to configuration may be made “on the fly” in response for example to the cost of an operation (e.g. length of time, energy cost, battery life, tariffs on cell phone data rate, costs based on data transferred, rates based on time, fees based on copies performed remotely, etc.) and/or the type of operation or operations being performed (e.g. watching a movie, long file copy, long computation, low battery, performing a backup, or combination of these).

In one embodiment, one operation O1 may be started at time t1 on a consumer electronics device (tablet, laptop, cell phone) that requires low performance with high memory capacity but for a short time. The memory configuration may be configured at t1 to use two classes of memory (a 2C system). Then a second operation O2 is started at time t2 (before the first operation O1 has finished) and O2 would ideally use a single-class memory system (1C system). The system, OS, CPU or buffer chip etc. may then decide at t2 to change (e.g. switch, modify, etc.) to a 1C system.

In other embodiments, given certain factors (e.g. speed required, CPU load, battery life remaining, video replay quality, etc.) the system may remain as 2C, as configured at t1. At time t3 the first operation O1 completes. Again at t3 the system may make a decision to change configuration. In this case the system may decide at t3 to switch from 2C to 1C.

FIG. 44

FIG. 44 shows a memory system with two-classes of memory: DRAM (in FIG. 44) and NAND flash (in FIG. 44), in accordance with one embodiment. As an option, the exemplary architecture of FIG. 44 may be implemented in the context (e.g. in combination with, as part of, together with, etc.) of the architecture and environment of the previous Figure(s), or any subsequent Figure(s).

In FIG. 44, the buffer chip (in FIG. 44) is shown separate from memory class 1 (in FIG. 44) and memory class 2 (in FIG. 44). In FIG. 44, the CPU (in FIG. 44) is connected to the buffer chip using Bus 1 (in FIG. 44), the memory system bus; the buffer chip is connected to memory Class 1 using Bus 2 (in FIG. 44); and the buffer chip is connected to memory class 2 using Bus 3 (in FIG. 44). In FIG. 44, memory class 1 is shown as DRAM, and memory class 2 is shown as flash.

In other embodiments: (1) memory class 1 may be any other form of memory technology (e.g. SDRAM, DDR, DDR2, DDR3, DDR4, GDDR, PRAM, MRAM, FeRAM, embedded DRAM, eDRAM, SRAM, etc.); (2) memory class 2 may also be any form of memory technology; (3) memory class 1 and memory class 2 may be the same memory technology but different in: (1) die size or overall capacity (e.g. memory class 1 may be 1 GB and memory class 2 may be 16 GB); (2) speed (e.g. memory class 1 may be faster than memory class 2); (3) bus width or other bus technology; (4) other aspect; (5) a combination of these.

In other embodiments, Bus 1, Bus 2 and Bus 3 may use one or more different bus technologies depending on the memory technology of memory class 1 and memory class 2. Although two memory classes are shown in FIG. 44, in some embodiments the buffer chip may have the capability to connect to more than two memory class technologies. In FIG. 44, memory class 1 and memory class 2 are shown as single blocks in the system diagram.

In some embodiments, both memory class 1 and memory class 2 may each be composed of several packages, components or die. In FIG. 44 both Bus 2 and Bus 3 are shown as a single bus. Depending on how many packages, components or die are used for memory class 1 and memory class 2, in some embodiments both Bus 1 and Bus 3 may be composed of several buses. For example Bus 2 may be composed of several buses to several components in memory class 1. In an embodiment, for example, that memory class 1 is composed of four 1 Gb DRAM die, there may be four buses connecting the buffer chip to memory class 1. In such an embodiment, these four buses may share some signals, for example: (1) buses may share some, all or none of the data signals (e.g. DQ, etc.); (2) buses may share some, all or none of the control signals and command signals (e.g. CS, ODT, CKE, CLK, DQS, DM, etc.); (3) buses may share some, all, or none of the address signals (e.g. bank address, column address, row address, etc.). Sharing of the bus or other signals may be determined by various factors, including but not limited to: (1) routing area and complexity (e.g. on a DIMM, on a motherboard, in a package, etc.); (2) protocol violations (e.g. data collision on a shared bus, timing violations between ranks determined by CS, etc.); (3) signal integrity (e.g. of multiple adjacent lines, caused by crosstalk on a bus, etc.); (4) any combination of these.

FIG. 45

FIG. 45 shows a package design containing a CPU (in FIG. 45) and two classes of memory, in accordance with one embodiment. As an option, the exemplary design of FIG. 45 may be implemented in the context (e.g. in combination with, as part of, together with, etc.) of the architecture and environment of the previous Figure(s), or any subsequent Figure(s).

In FIG. 45, memory class 1 (in FIG. 45) and memory class 2 (in FIG. 45) are stacked directly on top of CPU and electrically connected (e.g. logically coupled, etc.) using through-silicon vias (TSV) (in FIG. 45). In FIG. 45, there is no buffer chip or other interface device or interface devices shown explicitly. However, any of the previously described architectures (e.g. designs, system topologies, package techniques, package technologies, etc.) may be employed in order to electrically connect (e.g. couple, logically connect, etc.) CPU to memory class 1 and memory class 2 and/or to connect memory class 1 to memory class 2. For example, in one embodiment, one or more buffer chips may be embedded in the CPU, and/or memory class 1, and/or memory class 2. In other embodiments, one or more buffer chips may also be packaged in the stack in any location: (1) between CPU and memory class 2; (2) between memory class 1 and memory class 2 (3) between both CPU and memory class 2 as well as between memory class 1 and memory class 2; (4) combinations of these.

In FIG. 45, the stack of chips is shown in one particular order but other arrangements may be used depending on several factors: (1) mechanical (e.g. in one embodiment chips may be stacked in the order of their areal size, with larger chips at the bottom of the stack, etc.); (2) thermal (e.g. in one embodiment the chips with the higher heat dissipation may be placed at the bottom of the stack, nearest the solder balls that may conduct heat through a circuit board for example; or in other embodiments the chip with the highest heat dissipation may be placed at the top of the stack with a thermal slug (e.g. sheet or slug of copper, other metal, etc.) on top of the chip in order to better conduct heat to a heat sink that may be placed on top of the package, etc.).

In FIG. 45, the CPU is shown bonded to the substrate (in FIG. 45) using a flip-chip arrangement. In other embodiments, other packaging technologies (e.g. flip-chip, interposers, PoP, PiP, RDL, CSP, etc.) may be used.

FIG. 46

FIG. 46 shows details of page copying methods between memory classes in a memory system with multiple memory classes, in accordance with one embodiment.

As an option, the exemplary methods of FIG. 46 may be implemented in the context (e.g. in combination with, as part of, together with, etc.) of the architecture and environment of the previous Figure(s), or any subsequent Figure(s).

In FIG. 46 several examples of methods to copy pages are shown. Not all possible copying options, copying methods, or copying techniques are shown in FIG. 46, but those that are shown are representative of the options, methods, techniques etc. that may be employed in various embodiments.

In FIG. 46, memory class 1 (in FIG. 46) contains pages marked 1 to N. In FIG. 46, in one embodiment, memory class 2 (in FIG. 46) contains pages marked N+1, N+2, etc., as well as pages that are marked MFT, F1, F2, etc. In one embodiment, Page MFT represents a Master File Table or equivalent table that is part of an OS file system. In such an embodiment, the MFT may (and, in some embodiment, may) span more than one page but has been represented as a single page in FIG. 46 for simplicity. In FIG. 46, Page F1, Page F2, etc. represent files that may be in memory class 2 for one or more purposes (e.g. part of a memory-mapped filesystem, for demand paging, part of a filesystem cache, etc.). In FIG. 46, Page F1 (or Page F2, Page F3, etc.) may be a single file, part of a file or contain multiple files. Although only memory class 2 is shown in FIG. 46 as containing files and related tables, one or more files and related tables could also be present in memory class 1, but that has not been shown in FIG. 46 for simplicity.

In FIG. 46, step Copy 1 shows a page being copied from memory class 2 to memory class 1. In FIG. 46, step Copy 2 shows a page being copied, moved, or duplicated in memory class 1. In FIG. 46, step Copy 3 shows a page being copied from memory class 1 to memory class 2. In FIG. 46, step Copy 4 shows a copy from a page in memory class 1 to a file in memory class 2. In FIG. 46, step Copy 5 shows a file being copied, moved or duplicated in memory class 2.

In different embodiments the copy operations described may be triggered by various mechanisms including, but not limited to: (1) using commands from the CPU (or OS, etc.); (2) using commands from one or more buffer chips; (3) combinations of these.

FIG. 47

FIG. 47 shows part of a system and the connection of a buffer chip (in FIG. 47) to an SDRAM (in FIG. 47), in accordance with one embodiment.

FIG. 47 includes the delays of each component for a write to SDRAM. In FIG. 47, Address Bus 47-A1, Control Bus 47-C1, and Data Bus 47-D1 are connected from CPU to the buffer chip. In FIG. 47, Address Bus 47-A1D, Control Bus 47-C1D, and Data Bus 47-D1D are connected from buffer chip to DDRX SDRAM (e.g. DDR2, DDR3, DDR4 etc.). The block labeled d1 in FIG. 47 represents the delay (e.g. latency, etc.) added by the buffer chip to bus A1. The block labeled d3 in FIG. 47 represents the delay added by the buffer chip to bus D1.

In FIG. 47, the connection of a buffer chip between a CPU and DRAM may cause standard memory protocol (e.g. JEDEC standard, etc.) violations. The following Figures and their accompanying descriptions will explain how some embodiments may allow systems such as that shown in FIG. 47 to operate within the restrictions (e.g. timing parameters, specifications, etc.) of standard memory protocols.

FIG. 48

FIG. 48 shows the timing diagram for the connections between a buffer chip and a DRAM for a write to the SDRAM, in accordance with one embodiment.

In FIG. 48 a write command is placed on A1 and C1 at time t5. In FIG. 48, write data is placed on bus D1 at time t7. For the JEDEC standard DDR protocols (e.g. DDR2, DDR3, etc.) the write data is placed on the data bus at a later time than the command is placed on the address bus and control bus. The difference in time is the write latency and may be represented by the symbol WL or the symbol CWL. The difference between t7 and t5 (t7−t5) is the write latency as seen at the CPU (e.g. CPU memory controller, etc.). The latency as seen by the CPU is CLD. In FIG. 48, at time t6, the address and control information representing the delayed write command appears on bus MD and bus C1D. The difference between t6 and t5 (t6−t5) is equal to delay D4. Depending on the relative delays CLD and D4, the events at t6 and t7 may be reversed from that shown in FIG. 48. In FIG. 48, at time t8, the data appears on bus D1D. The difference between t8 and t7 (t8−t7) is equal to delay D3.

In the explanation that follows, the relationship between the delays in the system of FIG. 48, in accordance with various embodiments, are described.

FIG. 49

FIG. 49 shows the timing equations and relationships for the connections between a buffer chip and a DDR2 SDRAM for a write to the SDRAM as shown in FIG. 48, in accordance with one embodiment.

In FIG. 49, the memory controller in the CPU (not shown) may be configured to operate with DDR2 SDRAM. In FIG. 49, the relationship between read latency of a DDR2 SDRAM (RL, or CL for CAS latency) and the write latency (WL, or CWL) is fixed as follows: WL=RL−1. In this equation “1” represents one clock cycle and the units of RL and WL are clock cycles. The read latency of the DDR2 SDRAM is represented by d2=RL. Then the read latency as seen by the CPU, RLD, can be written in terms of RL and the delays of the buffer chip as follows: RLD=RL+d1+d3. In this equation, d1 represents the delay of the buffer chip for the address bus for reads. The write latency as of the DDR2 SDRAM, WL, can be written in terms of the write latency as seen by the CPU, WLD, and delays of the buffer chip: WL=WLD+d3−d4. In this equation d4 represents the delay of the buffer chip for the address bus for writes. The CPU enforces the same relationship between WLD and RLD as is true for the SDRAM values WL and RL: WLD=RLD−1. Thus, the following equation is true for the protocol between the buffer chip and DDR2 SDRAM: d4=2d3+d1.

This equation implies that the delay of the address bus (and control bus) depends on the type of command (e.g. read, write, etc.). Without this command-dependent delay, the interface between buffer chip and SDRAM may violate standard (e.g. JEDEC standard, etc.) timing parameters of the DDR2 SDRAM.

In various embodiments, logic that introduces a delay may be included in any of the buffer chips present in any designs that are described in other Figure(s) and that interface (e.g. connect, couple, etc.) the CPU to DDR2 SDRAM. In one embodiment, the memory controller and/or CPU may be designed to account for any timing issue caused by the presence of the buffer chip (and thus the equation relating WLD to RLD may no longer be a restriction). In such an embodiment, using a potentially non-standard design of CPU and/or memory controller, the design of the buffer chip may be simplified.

In other embodiments, the logic in the buffer chip may be used to alter the delay(s) of the bus(es) in order to adhere (e.g. obey, meet timing, etc.) to standard (e.g. JEDEC standard, etc.) timing parameters of the DDR2 SDRAM.

FIG. 50

FIG. 50 shows the timing equations and relationships for the connections between a buffer chip and a DDR3 SDRAM for a write to the SDRAM as shown in FIG. 48, in accordance with one embodiment.

In FIG. 50, the relationship between write latency and read latency is more complex than DDR2 and is as follows: WL=RL−K; where K is an integer (number of clock cycles). The relationship governing the buffer chip delays is then: d4=2d3+d1+(K−1). In various embodiments, the memory controller and/or CPU may follow the JEDEC DDR3 protocol, and in such embodiments the buffer chip may insert a command-dependent delay in the bus(es) (e.g. address bus, control bus, etc.) to avoid timing issues.

In other embodiments one or more buffer chips may be used. Such buffer chips may be the same or different. In such embodiments, for example, delays may be introduced by more than one buffer chip or by combinations of delays in different buffer chips.

In other embodiments, the delays may be inserted in one or more buses as relative delays (e.g. delay inserting a delay da in all buses but one with that one bus being delayed instead by a delay of (da+db) may be equivalent to (e.g. viewed as, logically equivalent to, etc.) a relative delay of db, etc.).

FIG. 51

FIG. 51 shows a system design for a memory system with multiple memory classes, SDRAM and NAND flash, in accordance with one embodiment.

In FIG. 51, the motherboard (in FIG. 51) (e.g. mainboard, chassis, PCB, etc.) is connected to a DIMM (in FIG. 51). Such an embodiment may be a design for a laptop, tablet, server or desktop type of machine. In other embodiments (e.g. consumer devices, cell phones, mp3 players, videocameras, etc.), there may not be a separation between motherboard and DIMM, instead both may be combined into a single printed-circuit board (PCB) for example. In FIG. 51 voltage supply VDD1 (in FIG. 51) may be the main supply voltage for the system (e.g. 5V, 12V, etc.). In FIG. 51, voltage regulator 1 (in FIG. 51) provides several functions including but not limited to the following: (1) regulates voltage VDD1 to voltage VDD3 (in FIG. 51); (2) provides charge and power management functions; (3) manages the supercapacitors 51-C1, 51-C2, and 51-C3.

In FIG. 51, the three supercapacitors 51-C1, 51-C2, and 51-C3 may be employed to provide backup power should the system fail. In the event of system failure, for example, the CPU may instruct the buffer chip (in FIG. 51) to effect a copy of data from volatile memory class 1 (DDR3 SDRAM in FIG. 51) to non-volatile memory class 2 (NAND flash in FIG. 51).

In FIG. 51, voltage VDD3 is provided to voltage regulator 2 (in FIG. 51) and as VDD6 (in FIG. 51) to NAND flash (in FIG. 51). For example, if the NAND flash is ONFi 2.0 NAND flash then VDD3=3.0V and VDD6=3.0V supplies the core voltage. The ONFi NAND flash also requires 1.8V for VCCQ or IO voltage. In FIG. 51, voltage regulator 2 may be used to regulate the VDD3=3.0V supply to VDD5=1.8V for the NAND flash IO supply. In FIG. 51, VDD2 (in FIG. 51) may be the mainboard DIMM supply, 1.5V, which is suitable for the DDR3 SDRAM. In FIG. 51, the buffer chip is shown operating from a separate supply VDD4 (in FIG. 51).

In one embodiment, VDD5 (In FIG. 51) may also be 1.8V and thus may be combined with or separate from the 1.8V NAND flash supply voltage VDD5.

In one embodiment, components may be used as follows: (1) 51-C1, 51-C2, and 51-C3 may be Illinois supercapacitors; each 2.5F capacitor may supply 8 mWh; each may be 10 mm by 23 mm; and the application may use three of these in parallel; (2) voltage regulator 1 may be an LTC4110 smart regulator, charger and management chip; in alternative embodiments, other similar components that may be used include: LTC3225 and LTC4616; (3) VDD3 may be supplied to a standard DIMM via an available pin (labeled Pin B in FIG. 51); one such available pin may be pin 236 used for VDDSPD (3.0V-3.6V) in a DDR3 DIMM; this pin 236 may carry 1A maximum; at 3V this may be 3 W maximum and this application may require 1.22 W on average from this pin; (4) the VDD2 supply may be the standard DIMM supply and may use multiple pins (but labeled as a single pin, Pin A, in FIG. 51 for simplicity); (4) the buffer chip may require 0.72 W on average which may be carried by the regulated VDD4 supply; (5) 8 GB of ONFi 2.0 NAND flash may require 3V VCC (core) and 1.8V VCCQ (10); the power demand may be approximately 5.1 mWh for backup and 0.5 W on average, which may be supplied by regulated VDD5 and regulated VDD6; (6) 8 GB of DDR3 SDRAM may require 1.5V (or 1.35V for low-power versions) at 2.9 mWh (read) and 7.3 mWh (write) for backup with 1 W average power demand; and this may be met with the VDD2 supply; (7) back-up may require approximately 37 seconds and 23 mWh for NAND flash, buffer chip and DDR3 SDRAM; and the average power drawn by the DIMM may be 2.2 W and maximum power (on DIMM read) may be 5.5 W.

FIG. 52

FIG. 52 shows a system including components used for copy involving modification of the CPU page table, in accordance with one embodiment.

In FIG. 52, the memory system comprises two memory classes. In FIG. 52, Page X (1) (in FIG. 52) is being copied to Page X (2) (in FIG. 52). In FIG. 52, the CPU (in FIG. 52) contains a Page Table (in FIG. 52). The Page Table contains a map from Virtual Address (VA) (in FIG. 52) to Physical Address (PA) (in FIG. 52). In FIG. 52, the CPU contains an RMAP Table (in FIG. 52). In Linux a reverse mapping (RMAP) is kept in a table (an RMAP table) that maintains a linked list containing pointers to the page table entries (PTEs) of every process currently mapping a given physical page. The Microsoft Windows OS versions contain a similar structure. The RMAP table essentially maintains the reverse mapping of a page to a page table entry (PTE) (in FIG. 52) and virtual address. In an OS, the RMAP table is used by the OS to speed up the page unmap path without necessarily requiring a scan of the process virtual address space. Using the RMAP table improves the unmapping of shared pages (because of the availability of the PTE mappings for shared pages), reduces page faults (because PTE entries are unmapped only when required), reduces searching required during page replacement as only inactive pages are touched, and there is only a low overhead involved in adding this reverse mapping during fork, page fault, mmap and exit paths. This RMAP table may be used, if desired, to find a PTE from a physical page number or PA. In FIG. 52, the CPU contains a Memory Allocator (in FIG. 52). The Memory Allocator may be used, if desired, to allocate a new page in the memory system.

FIG. 53

FIG. 53 shows a technique for copy involving modification of the CPU page table, in accordance with one embodiment.

In FIG. 53, the copy is triggered by a request from the memory system to the CPU to perform a copy. This is just one example of a copy. Other copy operations may be: (1) triggered by the CPU and passed to the memory system as a command with the copy being executed autonomously by the memory system; (2) triggered by the memory system and executed autonomously by the memory system; (3) triggered by the CPU and executed by the CPU; (4) combinations of these. FIG. 53 shows the following steps: (1) Step 1 is the entry to a method to swap two pages in the memory system (the same process may be used for other operations e.g. move, copy, transfer, etc.); (2) Step 2 uses the memory allocator in the CPU to allocate a new page in the memory system with address VA1. The new page could be in any of the memory classes in the memory system; (3) Step 3 maps the physical address (e.g. page number, etc.) of the page to be swapped (e.g. copied, moved, etc.) to the PTE using the RMAP table and determines address VA2; (4) Step 4 swaps (e.g. moves, copies, transfers, etc.) Page (1) to Page (2) using VA 1 and VA2; (5) Step 5 updates the Page Table; (6) Step 6 updates the Page Table cache or TLB; (7) Step 7 releases Page (1) for move, swap, etc. operations where the old page is no longer required.

FIG. 54

FIG. 54 shows a memory system including Page Table (in FIG. 54), buffer chip (in FIG. 54), RMAP Table (in FIG. 54), and Cache (in FIG. 54), in accordance with one embodiment.

In FIG. 54 in one embodiment the Page Table and RMAP Table may be integrated into the memory system. In FIG. 54 these components have been shown as separate from the buffer chip, memory class 1 (in FIG. 54) and memory class 2 (in FIG. 54). In one embodiment the Page Table, RMAP Table and Cache are integrated with the buffer chip. In other embodiments these components may be integrated with (or separate from) one or more of the following components shown in FIG. 54: (1) memory class 1; (2) memory class 2; (3) buffer chip.

In some embodiments, the Cache may be used to hold information contained in the Page Table and/or RMAP Table.

In FIG. 54, the presence of the Page Table allows the memory system to autonomously (e.g. without help from the CPU, OS, etc.) perform a mapping of VA (in FIG. 54) to PA (in FIG. 54). In FIG. 54 the presence of the RMAP Table allows the memory system to autonomously perform a mapping of PA to VA. These mapping functions are useful in page operations (e.g. move, copy, swap, transfer, etc.) that may be performed, for example, by the buffer chip.

FIG. 55

FIG. 55 shows a memory system access pattern, in accordance with one embodiment.

In FIG. 55, patterns of access to certain memory locations in a memory system are diagrammed. In FIG. 55, the X-axis represents page number within the memory system (with a page size of 4 kBytes). In FIG. 55, the X-axis represents the cache line number within a page (with a cache line size of 64 Bytes there are 64 cache lines in a 4-kByte page). By running memory traces it is often found there are certain hot spots in memory, marked in FIG. 55 by hot spots H1, H2, H3, and H4. Each of these hot spots represent a sequence of cache lines that are repeatedly accessed (e.g. frequently executed code routines, frequently accessed data, etc.) more frequently than other areas of memory.

FIG. 56

FIG. 56 shows memory system address mapping functions, in accordance with one embodiment.

In FIG. 56, the 32-bit Address (in FIG. 56) in a 32-bit system (e.g. machine (physical or virtual), CPU, OS, etc.) is shown divided into a 12-bit Offset and 30-bit Physical Page Number.

In FIG. 56, one embodiment of an address mapping uses Map (1) (in FIG. 56) shows how the Address may be mapped to the memory system. In FIG. 56, Map (1) the bits are as follows: (1) bits 0-2 correspond (e.g. map, or are used as, etc.) to the Byte Address (in FIG. 56) of the memory system; (2) bits 3-12 correspond to the Column Address (in FIG. 56) of the memory system; (3) bits 13-25 correspond to the Row Address (in FIG. 56) of the memory system; (4) bits 26-27 correspond to the Bank (in FIG. 56) of the memory system; and bits 28-31 correspond to the Rank (in FIG. 56) of the memory system.

In FIG. 56, Map (2) shows an embodiment that uses an alternative system address mapping to the memory system (e.g. the Bank address has moved in position from that shown in Map(1) in FIG. 56). Depending on several factors (e.g. type of memory access, type of program being executed, data patterns, etc.) the memory access patterns may favor one address mapping over another address mapping. For example, in some programs (e.g. modes of operation, etc.) Map (1) of FIG. 56 combined with the access pattern shown in FIG. 55 may result in better performance of the memory system (e.g. lower power, higher speed, etc.). This may be especially true when the memory system comprises multiple memory classes and, for example, it may be desired that the hot spots (as described in FIG. 55 for example) should remain in one class of memory.

In various embodiments, the address mapping function may thus be controlled as described, especially for memory systems with multiple memory classes.

FIG. 57

FIG. 57 shows a memory system that alters address mapping functions, in accordance with one embodiment.

In FIG. 57, the buffer chip (in FIG. 57) contains logic that may receive an address from the CPU (in FIG. 57) (e.g. from memory controller, etc.) and is capable of changing (e.g. swizzling, re-mapping, altering, etc.) the address mapping. In one embodiment, the address from the CPU may use Map (1) (in FIG. 57). In another embodiment, the buffer chip may change Map (1) to Map (2) (in FIG. 57).

The ability to change address mapping may be used in several ways. For example, if memory class 1 in FIG. 57 is a small but fast class of memory relative to the larger but slower memory class 2 (in FIG. 57), then, in one embodiment for example, one type of map may keep hot spots (as described in FIG. 55 and marked H1 to H4 in FIG. 57) in memory class 1.

In alternative embodiments: (1) the CPU (e.g. machine (virtual or physical), OS, etc.) may instruct (e.g. based on operating mode, by monitoring memory use, by determining memory hot spots, by pre-configured statistics for certain programs, etc.) the buffer chip to alter from Map (x) to Map (y), where Map (x) and Map (y) are arbitrary address mappings; (2) the buffer chip may configure the address mapping to Map (x) (where Map (x) is an arbitrary address map) based on memory use and/or other factors (e.g. power, wear-leveling of any or all memory classes, etc.); (3) different address maps may be used for any or all of the memory classes; (4) the memory classes may be identical but may use different memory maps; (5) and/or any combination of these.

FIG. 58

FIG. 58 illustrates an exemplary system 5800 in which the various architecture and/or functionality of the various previous embodiments may be implemented. As shown, a system 5800 is provided including at least one host processor 5801 which is connected to a communication bus 5802. The system 5800 also includes a main memory 5804. Control logic (software) and data are stored in the main memory 5804 which may take the form of random access memory (RAM).

The system 5800 also includes a graphics processor 5806 and a display 5808, e.g. a computer monitor.

The system 5800 may also include a secondary storage 5810. The secondary storage 5810 includes, for example, a hard disk drive and/or a removable storage drive, representing a floppy disk drive, a magnetic tape drive, a compact disk drive, etc. The removable storage drive reads from and/or writes to a removable storage unit in any desired manner.

Computer programs, or computer control logic algorithms, may be stored in the main memory 5804 and/or the secondary storage 5810. Such computer programs, when executed, enable the system 5800 to perform various functions. Memory 5804, storage 5810 and/or any other storage are possible examples of computer-readable media.

In one embodiment, the architecture and/or functionality of the various previous figures may be implemented in the context of the host processor 5801, graphics processor 5806, a chipset (e.g. a group of integrated circuits designed to work and sold as a unit for performing related functions, etc.), and/or any other integrated circuit for that matter.

Still yet, the architecture and/or functionality of the various previous figures may be implemented in the context of a general computer system, a circuit board system, a game console system dedicated for entertainment purposes, an application-specific system, and/or any other desired system. For example, the system 5800 may take the form of a desktop computer, lap-top computer, and/or any other type of logic. Still yet, the system 5800 may take the form of various other devices including, but not limited to, a personal digital assistant (PDA) device, a mobile phone device, a television, etc.

Further, while not shown, the system 5800 may be coupled to a network [e.g. a telecommunications network, local area network (LAN), wireless network, wide area network (WAN) such as the Internet, peer-to-peer network, cable network, etc.] for communication purposes.

GLOSSARY AND CONVENTIONS FOR DESCRIPTION OF FOLLOWING FIGURES

Memory devices with improved performance are required with every new product generation and every new technology node. However, the design of memory modules such as DIMMs becomes increasingly difficult with increasing clock frequency and increasing CPU bandwidth requirements yet lower power, lower voltage, and increasingly tight space constraints. The increasing gap between CPU demands and the performance that memory modules can provide is often called the “memory wall”. Hence, memory modules with improved performance are needed to overcome these limitations.

Memory devices (e.g. memory modules, memory circuits, memory integrated circuits, etc.) are used in many applications (e.g. computer systems, calculators, cellular phones, etc.). The packaging (e.g. grouping, mounting, assembly, etc.) of memory devices varies between these different applications. A memory module is a common packaging method that uses a small circuit board (e.g. PCB, raw card, card, etc.) often comprised of random access memory (RAM) circuits on one or both sides of the memory module with signal and/or power pins on one or both sides of the circuit board. A dual in-line memory module (DIMM) comprises one or more memory packages (e.g. memory circuits, etc.). DIMMs have electrical contacts (e.g. signal pins, power pins, connection pins, etc.) on each side (e.g. edge etc.) of the module. DIMMs are mounted (e.g. coupled etc.) to a printed circuit board (PCB) (e.g. motherboard, mainboard, baseboard, chassis, planar, etc.). DIMMs are designed for use in computer system applications (e.g. cell phones, portable devices, hand-held devices, consumer electronics, TVs, automotive electronics, embedded electronics, lap tops, personal computers, workstations, servers, storage devices, networking devices, network switches, network routers, etc.). In other embodiments different and various form factors may be used (e.g. cartridge, card, cassette, etc.).

The number of connection pins on a DIMM varies. For example: a 240 connector pin DIMM is used for DDR2 SDRAM, DDR3 SDRAM and FB-DIMM DRAM; a 184 connector pin DIMM is used for DDR SDRAM.

Example embodiments described in this disclosure include computer system(s) with one or more central processor units (CPU) and possibly one or more I/O unit(s) coupled to one or more memory systems that contain one or more memory controllers and memory devices. In example embodiments, the memory system(s) includes one or more memory controllers (e.g. portion(s) of chipset(s), portion(s) of CPU(s), etc.). In example embodiments the memory system(s) include one or more physical memory array(s) with a plurality of memory circuits for storing information (e.g. data, instructions, etc.).

The plurality of memory circuits in memory system(s) may be connected directly to the memory controller(s) and/or indirectly coupled to the memory controller(s) through one or more other intermediate circuits (or intermediate devices e.g. hub devices, switches, buffer chips, buffers, register chips, registers, receivers, designated receivers, transmitters, drivers, designated drivers, re-drive circuits, etc.).

Intermediate circuits may be connected to the memory controller(s) through one or more bus structures (e.g. a multi-drop bus, point-to-point bus, etc.) and which may further include cascade connection(s) to one or more additional intermediate circuits and/or bus(es). Memory access requests are transmitted by the memory controller(s) through the bus structure(s). In response to receiving the memory access requests, the memory devices may store write data or provide read data. Read data is transmitted through the bus structure(s) back to the memory controller(s).

In various embodiments, the memory controller(s) may be integrated together with one or more CPU(s) (e.g. processor chips, multi-core die, CPU complex, etc.) and supporting logic; packaged in a discrete chip (e.g. chipset, controller, memory controller, memory fanout device, memory switch, hub, memory matrix chip, northbridge, etc.); included in a multi-chip carrier with the one or more CPU(s) and/or supporting logic; or packaged in various alternative forms that match the system, the application and/or the environment. Any of these solutions may or may not employ one or more bus structures (e.g. multidrop, multiplexed, point-to-point, serial, parallel, narrow/high speed links, etc.) to connect to one or more CPU(s), memory controller(s), intermediate circuits, other circuits and/or devices, memory devices, etc.

A memory bus may be constructed using multi-drop connections and/or using point-to-point connections (e.g. to intermediate circuits, to receivers, etc.) on the memory modules. The downstream portion of the memory controller interface and/or memory bus, the downstream memory bus, may include command, address, write data, control and/or other (e.g. operational, initialization, status, error, reset, clocking, strobe, enable, termination, etc.) signals being sent to the memory modules (e.g. the intermediate circuits, memory circuits, receiver circuits, etc.). Any intermediate circuit may forward the signals to the subsequent circuit(s) or process the signals (e.g. receive, interpret, alter, modify, perform logical operations, merge signals, combine signals, transform, store, re-drive, etc.) if it is determined to target a downstream circuit; re-drive some or all of the signals without first modifying the signals to determine the intended receiver; or perform a subset or combination of these options etc.

The upstream portion of the memory bus, the upstream memory bus, returns signals from the memory modules (e.g. requested read data, error, status other operational information, etc.) and these signals may be forwarded to any subsequent intermediate circuit via bypass or switch circuitry or be processed (e.g. received, interpreted and re-driven if it is determined to target an upstream or downstream hub device and/or memory controller in the CPU or CPU complex; be re-driven in part or in total without first interpreting the information to determine the intended recipient; or perform a subset or combination of these options etc.).

In different memory technologies portions of the upstream and downstream bus may be separate, combined, or multiplexed; and any buses may be unidirectional (one direction only) or bidirectional (e.g. switched between upstream and downstream, use bidirectional signaling, etc.). Thus, for example, in JEDEC standard DDR (e.g. DDR, DDR2, DDR3, DDR4, etc.) SDRAM memory technologies part of the address and part of the command bus are combined (or may be considered to be combined), row address and column address are time-multiplexed on the address bus, and read/write data uses a bidirectional bus.

In alternate embodiments, a point-to-point bus may include one or more switches or other bypass mechanism that results in the bus information being directed to one of two or more possible intermediate circuits during downstream communication (communication passing from the memory controller to a intermediate circuit on a memory module), as well as directing upstream information (communication from an intermediate circuit on a memory module to the memory controller), possibly by way of one or more upstream intermediate circuits.

In some embodiments the memory system may include one or more intermediate circuits (e.g. on one or more memory modules etc.) connected to the memory controller via a cascade interconnect memory bus, however other memory structures may be implemented (e.g. point-to-point bus, a multi-drop memory bus, shared bus, etc.). Depending on the constraints (e.g. signaling methods used, the intended operating frequencies, space, power, cost, and other constraints, etc.) various alternate bus structures may be used. A point-to-point bus may provide the optimal performance in systems requiring high-speed interconnections, due to the reduced signal degradation compared to bus structures having branched signal lines, switch devices, or stubs. However, when used in systems requiring communication with multiple devices or subsystems, a point-to-point or other similar bus will often result in significant added cost (e.g. component cost, board area, increased system power, etc.) and may reduce the potential memory density due to the need for intermediate devices (e.g. buffers, re-drive circuits, etc.). Functions and performance similar to that of a point-to-point bus can be obtained by using switch devices. Switch devices and other similar solutions offer advantages (e.g. increased memory packaging density, lower power, etc.) while retaining many of the characteristics of a point-to-point bus. Multi-drop bus solutions provide an alternate solution, and though often limited to a lower operating frequency can offer a cost/performance advantage for many applications. Optical bus solutions permit significantly increased frequency and bandwidth potential, either in point-to-point or multi-drop applications, but may incur cost and space impacts.

Although not necessarily shown in all the Figures, the memory modules or intermediate devices may also include one or more separate control (e.g. command distribution, information retrieval, data gathering, reporting mechanism, signaling mechanism, register read/write, configuration, etc.) buses (e.g. a presence detect bus, an I2C bus, an SMBus, combinations of these and other buses or signals, etc.) that may be used for one or more purposes including the determination of the device and/or memory module attributes (generally after power-up), the reporting of fault or other status information to part(s) of the system, calibration, temperature monitoring, the configuration of device(s) and/or memory subsystem(s) after power-up or during normal operation or for other purposes. Depending on the control bus characteristics, the control bus(es) might also provide a means by which the valid completion of operations could be reported by devices and/or memory module(s) to the memory controller(s), or the identification of failures occurring during the execution of the main memory controller requests, etc.

As used herein the term buffer (e.g. buffer device, buffer circuit, buffer chip, etc.) refers to an electronic circuit that may include temporary storage, logic etc. and may receive signals at one rate (e.g. frequency, etc.) and deliver signals at another rate. In some embodiments, a buffer is a device that may also provide compatibility between two signals (e.g., changing voltage levels or current capability, changing logic function, etc.).

As used herein, hub is a device containing multiple ports that may be capable of being connected to several other devices. The term hub is sometimes used interchangeably with the term buffer. A port is a portion of an interface that serves an I/O function (e.g., a port may be used for sending and receiving data, address, and control information over one of the point-to-point links, or buses). A hub may be a central device that connects several systems, subsystems, or networks together. A passive hub may simply forward messages, while an active hub (e.g. repeater, amplifier, etc.) may also modify the stream of data which otherwise would deteriorate over a distance. The term hub, as used herein, refers to a hub that may include logic (hardware and/or software) for performing logic functions.

As used herein, the term bus refers to one of the sets of conductors (e.g., signals, wires, traces, and printed circuit board traces or connections in an integrated circuit) connecting two or more functional units in a computer. The data bus, address bus and control signals may also be referred to together as constituting a single bus. A bus may include a plurality of signal lines (or signals), each signal line having two or more connection points that form a main transmission line that electrically connects two or more transceivers, transmitters and/or receivers. The term bus is contrasted with the term channel that may include one or more buses or sets of buses.

As used herein, the term channel (e.g. memory channel etc.) refers to an interface between a memory controller (e.g. a portion of processor, CPU, etc.) and one of one or more memory subsystem(s). A channel may thus include one or more buses (of any form in any topology) and one or more intermediate circuits.

As used herein, the term daisy chain (e.g. daisy chain bus etc.) refers to a bus wiring structure in which, for example, device (e.g. unit, structure, circuit, block, etc.) A is wired to device B, device B is wired to device C, etc. In some embodiments the last device may be wired to a resistor, terminator, or other termination circuit etc. In alternative embodiments any or all of the devices may be wired to a resistor, terminator, or other termination circuit etc. In a daisy chain bus, all devices may receive identical signals or, in contrast to a simple bus, each device may modify (e.g. change, alter, transform, etc.) one or more signals before passing them on.

A cascade (e.g. cascade interconnect, etc.) as used herein refers to a succession of devices (e.g. stages, units, or a collection of interconnected networking devices, typically hubs or intermediate circuits—etc.) in which the hubs or intermediate circuits operate as logical repeater(s), permitting for example data to be merged and/or concentrated into an existing data stream or flow on one or more buses.

As used herein, the term point-to-point bus and/or link refers to one or a plurality of signal lines that may each include one or more termination circuits. In a point-to-point bus and/or link, each signal line has two transceiver connection points, with each transceiver connection point coupled to transmitter circuits, receiver circuits or transceiver circuits.

As used herein, a signal (or line, signal line, etc.) refers to one or more electrical conductors or optical carriers, generally configured as a single carrier or as two or more carriers, in a twisted, parallel, or concentric arrangement, used to transport at least one logical signal. A logical signal may be multiplexed with one or more other logical signals generally using a single physical signal but logical signal(s) may also be multiplexed using more than one physical signal.

As used herein, memory devices are generally defined as integrated circuits that are composed primarily of memory (storage) cells, such as DRAMs (Dynamic Random Access Memories), SRAMs (Static Random Access Memories), FeRAMs (Ferro-Electric RAMs), MRAMs (Magnetic Random Access Memories), Flash Memory and other forms of random access and related memories that store information in the form of electrical, optical, magnetic, chemical, biological or other means. Dynamic memory device types may include FPM DRAMs (Fast Page Mode Dynamic Random Access Memories), EDO (Extended Data Out) DRAMs, BEDO (Burst EDO) DRAMs, SDR (Single Data Rate) Synchronous DRAMs, DDR (Double Data Rate) Synchronous DRAMs, DDR2, DDR3, DDR4, or any of the expected follow-on devices and related technologies such as Graphics RAMs, Video RAMs, LP RAM (Low Power DRAMs) which are often based on the fundamental functions, features and/or interfaces found on related DRAMs.

Memory devices may include chips (die) and/or single or multi-chip or multi-die packages of various types, assemblies, forms, and configurations. In multi-chip packages, the memory devices may be packaged with other device types (e.g. other memory devices, logic chips, CPUs, hubs, buffers, intermediate devices, analog devices, programmable devices, etc.) and may also include passive devices (e.g. resistors, capacitors, inductors, etc.). These multi-chip packages may include cooling enhancements (e.g. an integrated heat sink, heat slug, fluids, gases, micromachined structures, micropipes, capillaries, combinations of these, etc.) that may be further attached to the carrier or another nearby carrier or other heat removal or cooling system.

Although not necessarily shown in all the Figures, memory module support devices (e.g. buffer(s), buffer circuit(s), buffer chip(s), register(s), intermediate circuit(s), power supply regulation, hub(s), re-driver(s), PLL(s), DLL(s), non-volatile memory, SRAM, DRAM, logic circuits, analog circuits, digital circuits, diodes, switches, LEDs, crystals, active components, passive components, combinations of these and other circuits, etc.) may be comprised of multiple separate chips (e.g. die, dice, integrated circuits, etc.) and/or components, may be combined as multiple separate chips onto one or more substrates, may be combined into a single package (e.g. using die stacking, multi-chip packaging, etc.) or even integrated onto a single device based on tradeoffs such as: technology, power, space, weight, cost, etc.

One or more of the various passive devices (e.g. resistors, capacitors, inductors, etc.) may be integrated into the support chip packages, or into the substrate, board, PCB, or raw card itself, based on tradeoffs such as: technology, power, space, cost, weight, etc. These packages may include an integrated heat sink or other cooling enhancements (e.g. such as those described above, etc.) that may be further attached to the carrier or another nearby carrier or other heat removal or cooling system.

Memory devices, intermediate devices and circuits, hubs, buffers, registers, clock devices, passives and other memory support devices etc. and/or other components may be attached (e.g. coupled, connected, etc.) to the memory subsystem and/or other component(s) via various methods including solder interconnects, conductive adhesives, socket structures, pressure contacts, electrical/mechanical/optical and/or other methods that enable communication between two or more devices (e.g. via electrical, optical, or alternate means, etc.).

The one or more memory modules (or memory subsystems) and/or other components/devices may be electrically/optically connected to the memory system, CPU complex, computer system or other system environment via one or more methods such as soldered interconnects, connectors, pressure contacts, conductive adhesives, optical interconnects and other communication and power delivery methods. Connector systems may include mating connectors (male/female), conductive contacts and/or pins on one carrier mating with a male or female connector, optical connections, pressure contacts (often in conjunction with a retaining and/or closure mechanism) and/or one or more of various other communication and power delivery methods. The interconnection(s) may be disposed along one or more edges of the memory assembly and/or placed a distance from an edge of the memory subsystem depending on such application requirements as ease of upgrade, ease of repair, available space and/or volume, heat transfer constraints, component size and shape and other related physical, electrical, optical, visual/physical access, requirements and constraints, etc. Electrical interconnections on a memory module are often referred to as contacts, pins, connection pins, tabs, etc. Electrical interconnections on a connector are often referred to as contacts or pins.

As used herein, the term memory subsystem refers to, but is not limited to: one or more memory devices; one or more memory devices and associated interface and/or timing/control circuitry; and/or one or more memory devices in conjunction with memory buffer(s), register(s), hub device(s), other intermediate device(s) or circuit(s), and/or switch(es). The term memory subsystem may also refer to one or more memory devices, in addition to any associated interface and/or timing/control circuitry and/or memory buffer(s), register(s), hub device(s) or switch(es), assembled into substrate(s), package(s), carrier(s), card(s), module(s) or related assembly, which may also include connector(s) or similar means of electrically attaching the memory subsystem with other circuitry. The memory modules described herein may also be referred to as memory subsystems because they include one or more memory device(s), register(s), hub(s) or similar devices.

The integrity, reliability, availability, serviceability, performance etc. of the communication path, the data storage contents, and all functional operations associated with each element of a memory system or memory subsystem may be improved by using one or more fault detection and/or correction methods. Any or all of the various elements of a memory system or memory subsystem may include error detection and/or correction methods such as CRC (cyclic redundancy code, or cyclic redundancy check), ECC (error-correcting code), EDC (error detecting code, or error detection and correction), LDPC (low-density parity check), parity, checksum or other encoding/decoding methods suited for this purpose. Further reliability enhancements may include operation re-try (e.g. repeat, re-send, etc.) to overcome intermittent or other faults such as those associated with the transfer of information, the use of one or more alternate, stand-by, or replacement communication paths to replace failing paths and/or lines, complement and/or re-complement techniques or alternate methods used in computer, communication, and related systems.

The use of bus termination is common in order to meet performance requirements on buses that form transmission lines, such as point-to-point links, multi-drop buses, etc. Bus termination methods include the use of one or more devices (e.g. resistors, capacitors, inductors, transistors, other active devices, etc. or any combinations and connections thereof, serial and/or parallel, etc.) with these devices connected (e.g. directly coupled, capacitive coupled, AC connection, DC connection, etc.) between the signal line and one or more termination lines or points (e.g. a power supply voltage, ground, a termination voltage, another signal, combinations of these, etc.). The bus termination device(s) may be part of one or more passive or active bus termination structure(s), may be static and/or dynamic, may include forward and/or reverse termination, and bus termination may reside (e.g. placed, located, attached, etc.) in one or more positions (e.g. at either or both ends of a transmission line, at fixed locations, at junctions, distributed, etc.) electrically and/or physically along one or more of the signal lines, and/or as part of the transmitting and/or receiving device(s). More than one termination device may be used for example if the signal line comprises a number of series connected signal or transmission lines (e.g. in daisy chain and/or cascade configuration(s), etc.) with different characteristic impedances.

The bus termination(s) may be configured (e.g. selected, adjusted, altered, set, etc.) in a fixed or variable relationship to the impedance of the transmission line(s) (often but not necessarily equal to the transmission line(s) characteristic impedance), or configured via one or more alternate approach(es) to maximize performance (e.g. the useable frequency, operating margins, error rates, reliability or related attributes/metrics, combinations of these, etc.) within design constraints (e.g. cost, space, power, weight, performance, reliability, other constraints, combinations of these, etc.).

Additional functions that may reside local to the memory subsystem and/or hub device include write and/or read buffers, one or more levels of memory cache, local pre-fetch logic, data encryption and/or decryption, compression and/or decompression, protocol translation, command prioritization logic, voltage and/or level translation, error detection and/or correction circuitry, data scrubbing, local power management circuitry and/or reporting, operational and/or status registers, initialization circuitry, performance monitoring and/or control, one or more co-processors, search engine(s) and other functions that may have previously resided in other memory subsystems. By placing a function local to the memory subsystem, added performance may be obtained as related to the specific function, often while making use of unused circuits within the subsystem.

Memory subsystem support device(s) may be directly attached to the same assembly (e.g. substrate, base, board, package, structure, etc.) onto which the memory device(s) are attached (e.g. mounted, connected, etc.) to a separate substrate (e.g. interposer, spacer, layer, etc.) also produced using one or more of various materials (e.g. plastic, silicon, ceramic, etc.) that include communication paths (e.g. electrical, optical, etc.) to functionally interconnect the support device(s) to the memory device(s) and/or to other elements of the memory or computer system.

Transfer of information (e.g. using packets, bus, signals, wires, etc.) along a bus, (e.g. channel, link, cable, etc.) may be completed using one or more of many signaling options. These signaling options may include such methods as single-ended, differential, time-multiplexed, encoded, optical or other approaches, with electrical signaling further including such methods as voltage or current signaling using either single or multi-level approaches. Signals may also be modulated using such methods as time or frequency, multiplexing, non-return to zero (NRZ), phase shift keying (PSK), amplitude modulation, combinations of these, and others. Voltage levels are expected to continue to decrease, with 1.8V, 1.5V, 1.35V, 1.2V, 1V and lower power and/or signal voltages of the integrated circuits.

One or more clocking methods may be used within the memory system, including global clocking, source-synchronous clocking, encoded clocking or combinations of these and/or other methods. The clock signaling may be identical to that of the signal lines, or may use one of the listed or alternate techniques that are more conducive to the planned clock frequency or frequencies, and the number of clocks planned within the various systems and subsystems. A single clock may be associated with all communication to and from the memory, as well as all clocked functions within the memory subsystem, or multiple clocks may be sourced using one or more methods such as those described earlier. When multiple clocks are used, the functions within the memory subsystem may be associated with a clock that is uniquely sourced to the memory subsystem, or may be based on a clock that is derived from the clock related to the signal(s) being transferred to and from the memory subsystem (such as that associated with an encoded clock). Alternately, a unique clock may be used for the signal(s) transferred to the memory subsystem, and a separate clock for signal(s) sourced from one (or more) of the memory subsystems. The clocks themselves may operate at the same or frequency multiple of the communication or functional frequency, and may be edge-aligned, center-aligned or placed in an alternate timing position relative to the signal(s).

Signals coupled to the memory subsystem(s) include address, command, control, and data, coding (e.g. parity, ECC, etc.), as well as other signals associated with requesting or reporting status (e.g. retry, etc.) and/or error conditions (e.g. parity error, etc.), resetting the memory, completing memory or logic initialization and other functional, configuration or related information etc. Signals coupled from the memory subsystem(s) may include any or all of the signals coupled to the memory subsystem(s) as well as additional status, error, control etc. signals, however generally will not include address and command signals.

Signals may be coupled using methods that may be consistent with normal memory device interface specifications (generally parallel in nature, e.g. DDR2, DDR3, etc.), or the signals may be encoded into a packet structure (generally serial in nature, e.g. FB-DIMM etc.), for example, to increase communication bandwidth and/or enable the memory subsystem to operate independently of the memory technology by converting the received signals to/from the format required by the receiving memory device(s).

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms (e.g. a, an, the, etc.) are intended to include the plural forms as well, unless the context clearly indicates otherwise.

The terms comprises and/or comprising, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

In the following description and claims, the terms include and comprise, along with their derivatives, may be used, and are intended to be treated as synonyms for each other.

In the following description and claims, the terms coupled and connected may be used, along with their derivatives. It should be understood that these terms are not necessarily intended as synonyms for each other. For example, connected may be used to indicate that two or more elements are in direct physical or electrical contact with each other. Further, coupled may be used to indicate that that two or more elements are in direct or indirect physical or electrical contact. For example, coupled may be used to indicate that that two or more elements are not in direct contact with each other, but the two or more elements still cooperate or interact with each other.

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.

As will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method or computer program product. Accordingly, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a circuit, component, module or system. Furthermore, aspects of the present invention may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.

FIG. 59-1A

FIG. 59-1A shows a system 59-100A for circuit cooperation, in accordance with one embodiment. As an option, the system 59-100A may be implemented in the context of the architecture and environment of any subsequent Figure(s). Of course, however, the system 59-100A may be implemented in any desired environment.

As shown, the system 59-100A includes a first semiconductor platform 59-102A including at least one first circuit 59-104A. Additionally, the system 59-100A includes at least one additional semiconductor platform 59-106A stacked with the first semiconductor platform 59-102A and including at least one additional circuit 59-108A. Further, the system 59-100A is operable such that the at least one first circuit 59-104A and the at least one additional circuit 59-108A cooperate to carry out at least one task.

In the context of the present description, a semiconductor platform refers to any platform including one or more substrates of one or more semiconducting material (e.g. silicon, germanium, gallium arsenide, and silicon carbide, etc.). Additionally, in various embodiments, the circuits may include a receiver circuit, a driver circuit, a termination circuit, an equalization circuit, and/or any other type of circuit. Furthermore, in one embodiment, the first semiconductor platform and/or the additional semiconductor platform may include multiple circuits. Additionally, in various embodiments, the system 59-100A may include any number of semiconductor platforms (e.g. 2, 3, 4, etc.).

In one embodiment, at least one of the first semiconductor platform or the additional semiconductor platform may include a memory semiconductor platform. The memory semiconductor platform may include any type of memory semiconductor platform such as random access memory (RAM) or dynamic random access memory (DRAM), etc. In various embodiments, the DRAM may take any form including, but not limited to, synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, etc.), graphics double data rate DRAM (GDDR, GDDR2, GDDR3, etc.), quad data rate DRAM (QDR DRAM), RAMBUS XDR DRAM (XDR DRAM), fast page mode DRAM (FPM DRAM), video DRAM (VDRAM), extended data out DRAM (EDO DRAM), burst EDO RAM (BEDO DRAM), multibank DRAM (MDRAM), synchronous graphics RAM (SGRAM), and/or any other DRAM or similar memory technology. In another embodiment, the memory semiconductor platform may include non-volatile memory (e.g. FeRAM, MRAM, and PRAM, etc.) and/or another form of volatile memory (e.g. SRAM, T-RAM, Z-RAM, and TTRAM, etc.).

Furthermore, in various embodiments, the system 59-100A may include at least one of a three-dimensional integrated circuit, a wafer-on-wafer device, a monolithic device, a die-on-wafer device, a die-on-die device, a three-dimensional package, and a three-dimensional package.

The additional semiconductor platform 59-106A may be in a variety of positions with respect to the first semiconductor platform 59-102A. For example, in one embodiment, the additional semiconductor platform 106A may be positioned above the first semiconductor platform 59-102A. In another embodiment, the additional semiconductor platform 106A may be positioned beneath the first semiconductor platform 59-102A. In still another embodiment, the additional semiconductor platform 59-106A may be positioned to the side of the first semiconductor platform 59-102A.

Further, in one embodiment, the additional semiconductor platform 106A may be in direct physical contact with the first semiconductor platform 59-102A. In another embodiment, the additional semiconductor platform 106A may be stacked with the first semiconductor platform 59-102A with at least one layer of material therebetween. In other words, in various embodiments, the additional semiconductor platform 106A may or may not be physically touching the first semiconductor platform 59-102A.

As shown in FIG. 59-1A, the first circuit 59-104A may be communicatively coupled to the at least one additional circuit 59-108A. In one embodiment, the first circuit 59-104A may be communicatively coupled to the additional circuit 59-108A utilizing at least one through-silicon via (TSV). Of course, in other embodiments, the first circuit 59-104A may be communicatively coupled to the additional circuit 59-108A utilizing any suitable coupling technique.

In one embodiment, at least one of the first circuit 59-104A or the additional circuit 59-108A may include at least one receiver circuit. In one embodiment, the receiver circuit may include a designated receiver circuit. In the context of the present description, a designated receiver circuit refers to any circuit that is determined to be a designated receiver for receiving commands and/or other data.

In another embodiment, the receiver circuit may include a secondary receiver circuit. In the context of the present description, a secondary receiver circuit refers to any circuit that is determined to be a secondary receiver for receiving commands and/or other data. In one embodiment, the secondary receiver, may include any receiver capable of receiving data from the designated receiver. Of course, in various embodiments, the first circuit 59-104A or the additional circuit 59-108A may include any combination of receiver circuits, driver circuits, termination circuits, and/or various other circuits.

In one embodiment, the first circuit 59-104A and the additional circuit 59-108A may both be directly coupled to a bus 59-110A that is capable of receiving signals from at least one processor 59-112A. In another embodiment, the first circuit 59-104A may be directly coupled to a bus that is capable of receiving signals from at least one processor, and the additional circuit 59-108A may be coupled to the first circuit 59-104A for receiving the signals, or a derivative thereof, via the first circuit 59-104A. In this case, the first circuit 59-104A may include a designated receiver, and the additional circuit 59-108A may include a secondary receiver.

In one embodiment, the first circuit 59-104A and the additional circuit 59-108A may each include a set of the same predetermined components. In another embodiment, the first circuit 59-104A and the additional circuit 59-108A may each include a set of the same predetermined components, where the predetermined components of the first circuit 59-104A are configured differently than the predetermined components of the additional circuit 59-108A. In this way, circuits with the same configuration and/or components may be utilized in fabrication (e.g. for cost savings, etc.).

In various embodiments, the predetermined components may include at least one driver, receiver, and/or any other component. In one embodiment, the predetermined components of the first circuit 59-104A may be configured with a first configuration that utilizes a first amount of power, and the predetermined components of the additional circuit 59-108A may be configured with a second configuration that utilizes a second amount of power that is less than the first amount of power.

In one embodiment, the system 59-100A may be operable such that the first circuit 59-104A and the additional circuit 59-108A cooperate to carry out at least one cooperation task. In the context of the present description, a cooperation task may refer to any task capable of being carried out by a first one or more circuits in cooperation with a second one of more circuits. The task may include any number of tasks, such as a task associated with a memory read, or a task associated with a memory write, etc.

Further, in one embodiment, the first circuit 59-104A may be operable to receive at least one first signal from the additional circuit 59-108A and subsequently generate at least one second signal that is a function of the at least one first signal. The signal may include any type of signal. Additionally, in one embodiment, the system 59-100A may include logic for receiving at least one first signal from the additional circuit 59-108A, logic for receiving at least one second signal from the first circuit 59-104A, and logic for subsequently generating at least one third signal that is a function of the at least one first signal and the at least one second signal.

Still yet, in one embodiment, the system 59-100A may include a plurality of additional semiconductor platforms stacked with the first semiconductor platform, where each includes at least one additional circuit. In this case, the first circuit may be operable to receive a plurality of first signals from the additional circuits of the additional semiconductors and subsequently generate at least one second signal that is a function of each of the first signals. In various embodiments, the function may include any type of function, such as a voting algorithm, a weighted voting algorithm, and a majority voting algorithm, etc.

More illustrative information will now be set forth regarding various optional architectures and features with which the foregoing techniques discussed in the context of any of the present or previous figure(s) may or may not be implemented, per the desires of the user. For instance, various optional examples and/or options associated with the configuration of the system 59-100A, the first circuit 59-104A, the second circuit 59-108A, the platforms 59-102A and 59-106A, and/or other optional features have been and will be set forth in the context of a variety of possible embodiments. It should be strongly noted, however, that such information is set forth for illustrative purposes and should not be construed as limiting in any manner. Any of such features may be optionally incorporated with or without the inclusion of other features described.

FIG. 59-1B

FIG. 59-1B shows an apparatus 59-100B using a memory system (in FIG. 59-1B) with a memory bus (in FIG. 59-1B) using signal encoding and with DIMMs using stacked memory die, in accordance with another embodiment. As an option, the apparatus 59-100B may be implemented in the context of the architecture and environment of the previous Figure and/or any subsequent Figure(s). Of course, however, the apparatus 59-100B may be implemented in the context of any desired environment.

FIG. 59-1B shows an apparatus 59-100B that comprises a memory system for use with a computing system (e.g. a mobile device, a computer, etc.). As shown, the CPU is coupled to a memory subsystem (in FIG. 59-1B) comprising one or more DIMMs (in FIG. 59-1B). Additionally, the CPU is coupled to a memory subsystem using a memory channel. In the present embodiment, the memory channel comprises a memory bus.

Further, as shown in FIG. 59-1B, each DIMM comprises one or more memory packages (in FIG. 59-1B). In various embodiments, each memory package may comprise one or more memory die. As an option, each memory die may, for example, be a DRAM die. In one embodiment, each memory package may comprise one or more stacked memory die.

As shown, the apparatus 59-100B comprises four DIMMs. In other embodiments any number of DIMMs may be used. Additionally, the apparatus 59-100B in FIG. 59-1B comprises a single memory bus, however, in other embodiments additional memory buses may be utilized. In one embodiment, the memory bus may include command, address, and data information (e.g. each possibly on their own bus, etc.), along with control information. The apparatus 59-100B in FIG. 59-1B comprises a single CPU, however, in other embodiments one or more CPUs may be used. In one embodiment, each CPU may be coupled to one or more memory buses.

In one embodiment, the apparatus 59-100B may include improvements to a memory system that uses stacked memory die. In various embodiments, the improvements may include new coding schemes for the memory bus, new I/O structures for the memory controller and memory die, new techniques for measuring the electrical characteristics of the memory channel, and/or new techniques for terminating the memory bus transmission lines.

In various embodiments, the one or more memory die may take any form including, but not limited to, DRAM, synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, etc.), graphics double data rate synchronous DRAM (GDDR SDRAM, GDDR2 SDRAM, GDDR3 SDRAM, etc.), quad data rate DRAM (QDR DRAM), RAMBUS XDR DRAM (XDR DRAM), fast page mode DRAM (FPM DRAM), video DRAM (VDRAM), extended data out DRAM (EDO DRAM), burst EDO RAM (BEDO DRAM), multibank DRAM (MDRAM), synchronous graphics RAM (SGRAM), FeRAM, MRAM, PRAM, SRAM, T-RAM, Z-RAM, TTRAM and/or any other similar non-volatile memory technology or technologies and/or volatile memory technology or technologies.

In various embodiments, the one or more memory die may use the same or different memory technology or memory technologies. Additionally, in various embodiments, the one or more memory die may use more than one memory technology on a die. In various embodiments, the one or more DIMMs may take any form including, but not limited to, an small-outline DIMM (SO-DIMM), unbuffered DIMM (UDIMM), registered DIMM (RDIMM), load-reduced DIMM (LR-DIMM), or any other form of mounting, packaging, assembly, etc.

FIG. 59-2A1

FIG. 59-2A1 shows a system including a memory bus that is multidrop bus (in FIG. 59-2A1) coupled to multiple receivers, in accordance with another embodiment. As an option, the system of FIG. 59-2A1 may be implemented in the context of the architecture and environment of the previous Figures and/or any subsequent Figure(s). Of course, however, the system of FIG. 59-2A1 may be implemented in the context of any desired environment.

FIG. 59-2A1 illustrates a representative system including a memory bus using JEDEC standard DDR3 technology. FIG. 59-2A1 shows a downstream memory bus that provides information flowing from a CPU 59-2 A1-100 to the memory devices (e.g. control information, write data, address, etc.).

As shown in FIG. 59-2A1, the CPU 59-2 A1-100 is coupled to the multidrop bus (in FIG. 59-2A1). The multidrop bus is coupled to multiple receivers (in FIG. 59-2A1). In one embodiment, the CPU 59-2 A1-100 may comprise a memory controller (not shown) coupled to the memory bus. In one embodiment, the memory controller may drive a capacitance presented by the memory bus.

In various embodiments, the capacitance of the memory bus may include the wire capacitance of the multidrop bus, multiple package capacitances, multiple pad capacitances, and input capacitances of the multiple input receivers. In one embodiment, the capacitance of the multi-drop bus may be responsible for a large fraction (e.g. 25%, etc.) of eye height loss. In the context of the present description, eye height loss is a measure of the difference between an ideal signal and the actual signal.

In order to simplify the connections and better explain the functions in FIG. 59-2A1 and in other figures in this description, not all of the devices (e.g. memory devices, memory packages, etc.) in a memory subsystem are necessarily shown. For example, in FIG. 59-2A1 only four die (59-2A1-D1, 59-2A1-D2, 59-2A1-D3, 59-2A1-D4) are shown. In one embodiment, in a memory subsystem of four DIMMs, there may be 36 memory packages on each DIMM (e.g. 18 packages on each side, etc.).

Further, each memory package may contain four die. Thus, in one embodiment, there may be 144 die in a memory subsystem of four DIMMs, rather than four die shown in FIG. 59-2A1. In one embodiment, each package may contribute 4 bits of data to a 72-bit data bus (assuming a 64-bit wide CPU data bus plus 8 bits of ECC). Additionally, the 4 groups of 18 packages may form 4 ranks. Further, each rank may be controlled by a chip select (CS) or other similar control signal(s) (possibly derived from other signal(s) etc.). Of course, in various embodiments, any number of groups, packages, ranks, etc. may be utilized.

FIG. 59-2A2

FIG. 59-2A2 shows a system including a memory bus that is a point-to-point bus (in FIG. 59-2A2) coupled to a designated receiver (in FIG. 59-2A2), in accordance with another embodiment. As an option, the system of FIG. 59-2A2 may be implemented in the context of the architecture and environment of the previous Figures and/or any subsequent Figure(s). Of course, however, the system of FIG. 59-2A2 may be implemented in the context of any desired environment.

In operation, the CPU 59-2A2-100 may drive a single designated receiver on each signal line. As shown, the designated receiver may be coupled to and drive a multidrop bus (in FIG. 59-2A2). Additionally, the multidrop bus may be coupled to multiple secondary receivers (in FIG. 59-2A2). A designated receiver is a receiver selected to receive a signal by itself on a bus. A designated receiver may then drive one or more secondary receivers. In one embodiment, the designated receiver may function as an intermediate circuit on the memory bus.

In one embodiment, the CPU 59-2A2-100 may comprise a memory controller (not shown) coupled to the memory bus. The memory controller may drive a capacitance presented by the memory bus. The capacitance of the memory bus may include the wire capacitance of the point-to-point bus, a single package capacitance, a single pad capacitance, and the input capacitance of the single designated receiver.

In the system of FIG. 59-2A2, the capacitance of the point-to-point bus may be considerably less than the capacitance of the multidrop bus shown in FIG. 59-2A1. Additionally, in the system of FIG. 59-2A2 the signal eye height may be much greater than the signal eye height of FIG. 59-2A1.

Further, in the system of FIG. 59-2A2, the signaling environment of the multidrop bus may be preferred (e.g. shorter physical conductor lengths, less electrical noise, less parasitic coupling, less capacitance, etc.) over the multidrop bus in FIG. 59-2A1. Additionally, the signal received by the secondary receivers may be better (e.g. less noisy, more ideal, etc.) than the signals received by the receivers in FIG. 59-2A1. Because of the lower noise and improved signal quality of the system of FIG. 59-2A2, it may be possible to operate the secondary receivers at a lower power than the power required to operate the receivers in FIG. 59-2A1.

Still yet, the power required and consumed by each of the multiple secondary receivers of the system in FIG. 59-2A2, may be less than the power required and consumed by each receiver in FIG. 59-2A1. Additionally, the total power consumed by the input receivers (e.g. single designated receiver and secondary receivers, etc.) may be less than the total power consumed by the multiple input receivers in FIG. 59-2A1.

In one embodiment, the single memory bus may comprise command, address, data, control (and possibly other) buses. In another embodiment, a designated receiver may be used for any or all of the signals that are part of the downstream memory bus. For example, a designated receiver may be used for each command signal, each address signal, each write data signal, and/or each control signal. In one embodiment, each memory package may use a designated receiver. For example, the bottom die in a multiple die stack may include the designated receiver. In other embodiments there may be more than one designated receiver. For example, a designated receiver may be used for (or used in, etc.) a portion (e.g. rank, bank, slice, etc.) of memory.

In another embodiment, there may be more than one designated receiver on one or more die with more than one designated receiver being active at one time. For example, a very large memory die may be split into portions with each portion having a designated receiver.

In another embodiment, there may be more than one designated receiver on one or more die, but with only one designated receiver being active at one time. Thus, for example, portions of a large memory die, including a designated receiver, may be controlled (e.g. shut off, powered-down, placed in a low-power state, etc.) to save power in a system.

In another embodiment, there may be more than one designated receiver on one or more die, but with different designated receivers being activated at different times. Thus, for example, on a large memory die designated receiver(s) in one area of a die may be powered-up for an access while other designated receiver(s) may be controlled (e.g. shut off, powered-down, placed in a low-power state, etc.) to save power in a system. The number and location (on a die) of active designated receivers may depend on the access performed.

In one embodiment, there may be more than one designated receiver on one or more die, but with different designated receivers on different die being activated at different times. Thus, for example, designated receiver(s) on one die may be powered-up for an access while other designated receiver(s) on other die may be controlled (e.g. shut off, powered-down, placed in a low-power state, etc.) to save power in a system. In one embodiment, the number and location of active designated receivers (across multiple die) may depend on the access performed.

In various embodiments, combinations of these techniques for controlling the designated receiver(s) on one or multiple die may be used. In various embodiments, the four die shown in FIG. 59-2A2 may belong to a single rank or may be split between ranks (e.g. one in each of four ranks, or two in each of two ranks, etc.). Further, in various embodiments the four die shown in FIG. 59-2A2 may be in a single package or multiple packages.

In one embodiment, portions of the memory subsystem may be formed using techniques other than ranks controlled by a chip select. For example, in one embodiment, a signal (e.g. select, enable, power on, etc.) may be decoded from address signals and used to address (e.g. turn on, enable, engage, etc.) portions of the memory subsystem by package (e.g. at the package level, etc.), by rank, by die, by portions of the die, etc.

In various embodiments, different numbers of die (e.g. 2, 8, 16, or any number, etc.) may be used with a designated receiver to form a group of interconnected die of any number. In one embodiment, the number of the group of interconnected die from a perspective of the system (e.g. CPU etc.) may be different than the physical number of die [e.g. buffer chip(s) may be used together with memory chips, spare chips may be packaged with other chips, etc.].

FIG. 59-2A3

FIG. 59-2A3 shows a system including a memory bus that is a point-to-point bus coupled to a designated receiver, in accordance with another embodiment. As an option, the system of FIG. 59-2A3 may be implemented in the context of the architecture and environment of the previous Figures and/or any subsequent Figure(s). Of course, however, the system of FIG. 59-2A3 may be implemented in the context of any desired environment.

In FIG. 59-2A3 System 1 uses a multidrop memory bus. In FIG. 59-2A3 System 1 (in FIG. 59-2A3) uses two receivers on the same bus. In FIG. 59-2A3 the memory bus has a parasitic capacitance comprising 59-2A3-C1 and 59-2A3-C2.

In FIG. 59-2A3 System 2 uses a point-to-point bus and a designated receiver 59-2A3-D1. In FIG. 59-2A3 the memory bus has a parasitic capacitance comprising 59-2A3-C1. In FIG. 59-2A3 the parasitic capacitance 59-2A3-C2 is hidden (e.g. isolated, etc.) behind the designated receiver 59-2A3-D1.

FIG. 59-2B

FIG. 59-2B shows a memory system with a designated receiver (in FIG. 59-2B) at the bottom of a multiple die stack, in accordance with another embodiment. As an option, the system of FIG. 59-2B may be implemented in the context of the architecture and environment of the previous Figures and/or any subsequent Figure(s). Of course, however, the system of FIG. 59-2B may be implemented in the context of any desired environment.

In the system of FIG. 59-2B, the multiple die stack includes four memory circuits (59-2B-D1, 59-2B-D2, 59-2B-D3, 59-2B-D4) in a single package. In one embodiment, communication between each die in the multiple die stack may be accomplished using a plurality of through-silicon vias. The use of TSVs may allow many more connections between die than would otherwise be possible using other connection techniques (e.g. wire bonding, etc.). In one embodiment, the TSVs may be used to connect the designated receiver on the bottom die to secondary receivers (in FIG. 59-2B) in the remaining die. In operation, the designated receiver may drive a multidrop bus. In one embodiment, the designated receiver may operate as an intermediate circuit on the memory bus (in FIG. 59-2B).

In one embodiment, there may be one or more additional layers [e.g. a passive layer, a spacer, a re-distribution layer (RDL), etc.] between each die in the multiple die stack. In various embodiments, the designated receiver(s) may be located at any position in the multiple die stack. In one embodiment, there may be more than one designated receiver within the multiple die stack.

In another embodiment, there may be more or less than four die in the stack contained within the package. Additionally, in another embodiment, one or more of the die in the multiple die stack may be spare die that are used, for example, when one or more die(s) in the multiple die stack are tested and found defective or otherwise need to be replaced.

In another embodiment, there may be more than one package in the memory system. Further, there may be more than one multiple die stack in a package. As an option, one or more die may contain more than one type of memory circuit.

FIG. 59-2C

FIG. 59-2C shows a memory system comprising a buffer chip (59-2C-D1) (e.g. logic chip, designated memory chip, buffer, etc) and four memory chips (59-2C-D2, 59-2C-D3, 59-2C-D4, 59-2C-D5) and using a downstream memory bus (in FIG. 59-2C) including command, address, and control buses with designated receivers (in FIG. 59-2C), in accordance with another embodiment. As an option, the system of FIG. 59-2C may be implemented in the context of the architecture and environment of the previous Figures and/or any subsequent Figure(s). Of course, however, the system of FIG. 59-2C may be implemented in the context of any desired environment.

As shown in FIG. 59-2C, the memory bus may use zero, one, two, or three sets of designated receivers within a multiple die stack. In one embodiment, each set of designated receivers may be used to receive a portion of the memory bus (e.g. command, data, control, etc.). Additionally, each of the sets of designated receivers may be coupled to a portion of the downstream memory bus. Further, each portion of the memory bus may be coupled to a CPU (in FIG. 59-2C).

As shown in FIG. 59-2C, each portion of the memory bus may be one-directional or bidirectional. In various embodiments, each designated receiver may receive command (CMD) (in FIG. 59-2C), address (ADDR) (in FIG. 59-2C), control (CTRL) (in FIG. 59-2C), or transmit (for read commands) and receive (for write commands) data (DATA).

In FIG. 59-2C, a designated receiver has been shown on each portion of the buses. In various embodiments any number of receivers may be used on any or all portions of the actual buses present for any given memory technology. Thus, for example, in JEDEC standard DDR2 SDRAM memory technology, any or all of the following signals may use a designated receiver: address (e.g. A0-A12 for a 256 Mb part, etc.); bank address (e.g. BA0-BA1, etc.); command (CS#, RAS#, CAS#, WE#, etc.); control (e.g. CKE, CK, CK#, ODT, etc.); data (e.g. DQ[15:0], etc.); masks and strobes (e.g. DM, DQS, DQS#, LDQS, LDQS#, UDQS, UDQS#, etc.); other address, command, data, or control signals; etc. For other memory technologies (e.g. DDR3, DDR4, etc.) there may be additional signals that may be used with designated receivers (e.g. additional address signals, data signals, control signals, reset signals, error signals, etc.).

In FIG. 59-2C, the DATA portion of the memory bus has not been shown. However, in one embodiment, a fourth set of designated receivers may also be used for the downstream portion of the DATA bus (e.g. for write data).

In different embodiments, any or all of the designated receiver(s) may function as intermediate circuit(s) on the memory bus.

FIG. 59-3A

FIG. 59-3A shows a system comprising a designated receiver (59-3A-D1A); receivers 59-3A-D1B, 59-3A-D1C, 59-3A-D1D, 59-3A-D1E; receivers 59-3A-D2A, 59-3A-D3A, 59-3A-D4A, 59-3A-D5A; and including a memory bus (in FIG. 59-3A) that is a point-to-point bus coupled to a designated receiver (in FIG. 59-3A) that drives secondary receivers using point-to-point wiring (in FIG. 59-3A), in accordance with another embodiment. As an option, the system of FIG. 59-3A may be implemented in the context of the architecture and environment of the previous Figures and/or any subsequent Figure(s). Of course, however, the system of FIG. 59-3A may be implemented in the context of any desired environment.

As shown in FIG. 59-3A, a designated receiver on a memory bus is coupled to a CPU (in FIG. 59-3A). In one embodiment, the designated receiver may be coupled to one or more secondary receivers using point-to-point wiring. Furthermore, the designated receiver may operate as an intermediate circuit on the memory bus. In one embodiment, the designated receiver and one or more secondary receivers may be coupled using TSVs.

In one embodiment, the designated receiver on die 59-3A-D1 may re-drive signals to one or more secondary receivers. Additionally, in one embodiment, the secondary receivers may be on other (i.e. different than the die that contains the designated receiver) dies 59-3A-D2, 59-3A-D3, 59-3A-D4, 59-3A-D5, etc. within a multiple die stack. In various embodiments, die 59-3A-D1 may be a memory circuit or may be an intermediate circuit (e.g. buffer, hub, etc.). Die 59-3A-D1 may be the same or different from other die 59-3A-D2, 59-3A-D3, 59-3A-D4, 59-3A-D5 etc. in the multiple die stack.

Various embodiments are contemplated with zero, one, two, three or more sets of designated receivers within a multiple die stack. In various embodiments, each of these designated receivers may receive signals on any portion of the memory bus (e.g. CMD, ADDR, CTRL, DATA, etc.) separately. Further, in one embodiment, a combination of point-to-point and multidrop buses may be used behind (e.g. downstream, etc.) the designated receiver(s) using elements of the structures shown in FIG. 59-2C and in FIG. 59-3A in combination.

FIG. 59-3B

FIG. 59-3B shows a system including a memory bus (in FIG. 59-3B) that is a point-to-point bus coupled to a designated receiver that drives secondary receivers using point-to-point wiring, in accordance with another embodiment. As an option, the system of FIG. 59-3B may be implemented in the context of the architecture and environment of the previous Figures and/or any subsequent Figure(s). Of course, however, the system of FIG. 59-3B may be implemented in the context of any desired environment.

FIG. 59-3B shows that, in one embodiment, the receivers on all die (59-3B-D1, 59-3B-D2, etc.) may include identical components and configuration capability (e.g. for simplicity, to save cost, etc.). In one embodiment, the designated receiver (formed from 59-3B-D1A and 59-3B-D1B, with 59-3B-D1C being used to re-drive the signals between die) may be coupled differently than the secondary receiver(s) (formed by 59-3B-D2A and 59-3B-D2B with 59-3B-D2C, the re-driver, not being required/used) without changing anything between the dies. In one embodiment, the designated receiver may use a higher-power first stage (59-3B-D1A on die 1 which is used; and 59-3B-D2A on die 2 which may not be required/used and may be placed in a low-power mode or even bypassed) to perform more demanding tasks. However, the secondary receivers may not use that high-power first stage (e.g. due to lack of necessity, etc.).

In various embodiments, the circuits shown in FIG. 59-3B may be communicatively coupled and/or configured in different manners. For example, in one embodiment, 59-3B-D2C may be used to re-drive the signal from die 59-3B-D2 just like 59-3B-D1C was used to re-drive from die 59-3B-D1. Of course, in various embodiments, any number of configurations may be utilized.

FIG. 59-3C

FIG. 59-3C shows a system including a memory bus that is a point-to-point bus coupled to a designated receiver that drives secondary receivers using point-to-point wiring, in accordance with another embodiment. As an option, the system of FIG. 59-3C may be implemented in the context of the architecture and environment of the previous Figures and/or any subsequent Figure(s). Of course, however, the system of FIG. 59-3C may be implemented in the context of any desired environment.

As shown in FIG. 59-3C, a designated receiver on a memory bus is coupled to a CPU. In one embodiment, the designated receiver may be coupled to one or more secondary receivers using point-to-point wiring. Furthermore, the designated receiver may operate as an intermediate circuit on the memory bus. In one embodiment, the designated receiver and one or more secondary receivers may be coupled using TSVs.

In one embodiment, the designated receiver on die 59-3C-D1 may re-drive signals to one or more secondary receivers. Additionally, in one embodiment, the secondary receivers may be on other dies 59-3C-D2, 59-3C-D3, 59-3C-D4, 59-3C-D5 etc. within a multiple die stack. In various embodiments, die D1 may be a memory circuit or may be another intermediate circuit (e.g. buffer, hub, etc.). In various embodiments, die 59-3C-D1 may be the same or different from other die 59-3C-D2, 59-3C-D3, 59-3C-D4, 59-3C-D5 etc. in the multiple die stack.

Various embodiments are contemplated with zero, one, two, three or more sets of designated receivers within a multiple die stack. In various embodiments, each of these designated receivers may receive signals on any portion of the memory bus (e.g. CMD, ADDR, CTRL, DATA, etc.) separately. Further, in one embodiment, a combination of point-to-point and multidrop buses may be used behind (e.g. downstream, etc.) the designated receiver(s) using elements of the structures shown in FIG. 59-2C and in FIG. 59-3C in combination.

FIG. 59-4A1

FIG. 59-4A1 shows a system including a memory bus (in FIG. 59-4A1) that is a multidrop bus coupled to a target receiver and multiple auxiliary receivers, in accordance with another embodiment. As an option, the system of FIG. 59-4A1 may be implemented in the context of the architecture and environment of the previous Figures and/or any subsequent Figure(s). Of course, however, the system of FIG. 59-4A1 may be implemented in the context of any desired environment.

As shown in FIG. 59-4A1, the memory system includes a multiple die stack in which all four die may be used for receiving, in accordance with one embodiment. As shown, in one embodiment, a target receiver 59-4A1-T1 may be on die 59-4A1-D1. The target receiver is the receiver for which the signal is intended. In the current embodiment, the target receiver and die 59-4A1-D1 may be the intended recipient of signal 59-4A1-S1 on the memory bus. As shown further in FIG. 59-4A1, three auxiliary receivers (59-4A1-A2, 59-4A1-A3, 59-4A1-A4) are on the other three die (59-4A1-D2, 59-4A1-D3, 59-4A1-D4) in the multiple die stack.

In FIG. 59-4A1 note that an auxiliary receiver receives the same signal as the target receiver but is not the intended signal recipient. The auxiliary receiver typically acts to help the target receiver in some way. Note carefully the difference between an auxiliary receiver and a secondary receiver. Typically the input of an auxiliary receiver is one the same bus as the input of a target receiver. Typically the input of a secondary receiver is on the same bus as the output of a designated receiver.

Note also that in different embodiments a target receiver could be a designated receiver and a designated receiver could be a target receiver. In general, this description uses the convention that a designated receiver is used with one or more secondary receivers. In general, this description uses the convention that a target receiver is used with one or more auxiliary receivers.

In operation, as shown in FIG. 59-4A1, auxiliary receivers 59-4A1-A2, 59-4A1-A3, 59-4A1-A4 may sample signal 59-4A1-S1 and communicate results 59-4A1-SA2, 59-4A1-SA3, 59-4A1-SA4 to die 59-4A1-D1. In one embodiment, a majority vote circuit 59-4A1-M1 on die 59-4A1-D1 may determine the value of signal 59-4A1-S1 using inputs from 59-4A1-T1 and signals 59-4A1-SA2, 59-4A1-SA3, 59-4A1-SA4. Although FIG. 59-4A1 shows the target receiver on die 59-4A1-D1, in various embodiments, a target receiver may be located on any die within the stack depending on the intended recipient of signal 59-4A1-S1.

FIG. 59-4A2

FIG. 59-4A2 shows a system including a die (59-4A2-D1), in accordance with another embodiment. As an option, the system of FIG. 59-4A2 may be implemented in the context of the architecture and environment of the previous Figures and/or any subsequent Figure(s). Of course, however, the system of FIG. 59-4A2 may be implemented in the context of any desired environment.

FIG. 59-4A2 shows one embodiment illustrating how a die may be selected using a chip select (CS) (in FIG. 59-4A2) signal. In this way, each die may determine whether it is to be a target receiver or an auxiliary receiver.

In one embodiment, the switches 59-4A2-SW1 and 59-4A2-SW2 controlled by CS may operate to switch in or switch out the majority vote circuit 59-4A2-M1 on different die. For example, the switches 59-4A2-SW1 and 59-4A2-SW2 controlled by CS may operate to switch in or switch out the majority vote circuit 59-4A2-M1 on the die associated with a target receiver.

In one embodiment, 59-4A2-X1 may be a control and memory (e.g. as in stored state) function (e.g. programmed by control signals on the memory channel, or programmed by addressing and writing special locations in memory, etc.). In one embodiment, 59-4A2-X1 may function to set up the receiver 59-4A2-T1 if, for example, the sampling time needs to be changed (e.g. relative to the clock edge, etc.).

In various embodiments, 59-4A2-T1 may be the designated receiver on one die and the auxiliary receiver on other dies. Additionally, in various embodiments, 59-4A2-T1 may not be configured the same way when it is a target receiver and when it is an auxiliary receiver. In one embodiment, the configuration of target receiver and auxiliary receiver functions may be accomplished by programming 59-4A2-X1 for each receiver.

In another embodiment, a majority vote circuit may not be used as 59-4A2-M1. For example, in one embodiment, a digital signal processor may be utilized as 59-4A2-M1. In various embodiments, any other logic circuit, or logic function (e.g. programmable function, fuzzy logic, etc.), processor, etc. may be utilized as 59-4A2-M1.

Further, in the case that a majority vote circuit may is used as 59-4A2-M1, each receiver signal may not necessarily have to be equally weighted in order to make a decision. Additionally, in one embodiment, the chip select 59-4A2-CS signal from the CPU or memory controller may not necessarily be used. For example, any other signal(s) may be utilized either from the system (CPU, etc.) or decoded from information (e.g. combination of multiple signals, etc.) on the memory bus.

FIG. 59-4A3

FIG. 59-4A3 shows a system including a plurality of die, in accordance with another embodiment. As an option, the system of FIG. 59-4A3 may be implemented in the context of the architecture and environment of the previous Figures and/or any subsequent Figure(s). Of course, however, the system of FIG. 59-4A3 may be implemented in the context of any desired environment.

As shown in FIG. 59-4A3, a particular die (e.g. 59-4A3-D1 the die electrically closest to the CPU, etc.) may be the designated receiver and the signals may be routed via TSVs to the target die (e.g. which might be 59-4A3-D2, 59-4A3-D3, 59-4A3-D4, 59-4A3-D5 in FIG. 59-4A3, etc.). In FIG. 59-4A3, 59-4A3-D1 is different from 59-4A3-D2, 59-4A3-D3, 59-4A3-D4, 59-4A3-D5 but, in another embodiment, the target receiver may also be 59-4A3-D1 if 59-4A3-D1 is the same as 59-4A3-D2, etc.

FIG. 59-4A3 shows a point-to-point bus behind D1A. However, in another embodiment, a multidrop or point-to-point bus may be utilized behind D1A. In another embodiment, combinations of point-to-point and multidrop may be used, if stack is big enough.

In another embodiment, only a subset of the die in the stack may be auxiliary receivers. For example, in one embodiment 4 die may be available but only 2 die may be needed. Thus, in one embodiment, n receivers may be utilized out of a group of m receivers in any permutation or combination thereof, where m is greater than or equal to n.

FIG. 59-4A4

FIG. 59-4A4 shows a system including a plurality of die, in accordance with another embodiment. As an option, the system of FIG. 59-4A4 may be implemented in the context of the architecture and environment of the previous Figures and/or any subsequent Figure(s). Of course, however, the system of FIG. 59-4A4 may be implemented in the context of any desired environment.

As shown in FIG. 59-4A4, TSVs may be utilized to make all the necessary connections between die. Although die 59-4A4-D1 is shown to be different from 59-4A4-D2, 59-4A4-D3, 59-4A4-D4, 59-4A4-D5, in another embodiment, 59-4A4-D1 may be the same as 59-4A4-D2, 59-4A4-D3, 59-4A4-D4, 59-4A4-D5.

In one embodiment, components and/hardware may be positioned between the die, such as interposers, spacers, or redistribution layers (RDLs), etc. In the context of the present description, an RDL refers to a PCB (e.g. a miniature PCB, deposited/etched/patterned layer(s), interposer, etc.) that may be positioned on top of a die. In one embodiment, RDLs between 59-4A4-D2 and 59-4A4-D3, 59-4A4-D3 and 59-4A4-D4, 59-4A4-D4 and 59-4A4-D5 may be the same (e.g. with some connections just left unused, etc.).

FIG. 59-4A5

FIG. 59-4A5 shows a system including a plurality of die (D1, D2, D3, D4, etc.), in accordance with another embodiment. As an option, the system of FIG. 59-4A5 may be implemented in the context of the architecture and environment of the previous Figures and/or any subsequent Figure(s). Of course, however, the system of FIG. 59-4A5 may be implemented in the context of any desired environment.

As shown in FIG. 59-4A5, TSVs (in FIG. 59-4A5) may be utilized to make all the necessary connections between die. Furthermore, in one embodiment, spacers (e.g. RDLs, interposers, etc.) may be positioned between die.

In one embodiment the TSV diameter may be 10-30 microns, with TSV depth of 50-100 microns, TSV aspect ratio of 3:1-5:1, TSV pitch of 75-100 microns, and TSV density of several hundred or more per die.

In different embodiments the TSV may or may not form a continuous connection through any interposer, spacer, or RDL layers.

FIG. 59-4B

FIG. 59-4B shows an eye diagram for a signal in a memory system using multiple auxiliary receivers to sample the signal, in accordance with one embodiment.

In FIG. 59-4B, a signal S1 (e.g. signal S1 from FIG. 59-4A1, etc.), which is represented by the eye diagram, may be sampled at, for example, sampling times ts1, ts2, ts3, ts4, ts5. In one embodiment, receivers [e.g. T1, A2, A3, A4 on die D1, D2, D3, and D4 in FIG. 59-4A1, etc.) may all sample signal S1 at time ts3 (i.e. tD1=tD2=tD3=tD4=ts3). In another embodiment, the timing of the signal sampling may be offset between each receiver (e.g. tD1=ts1; tD2=ts2; tD3=ts4; tD4=ts5). In various other embodiments, different permutations and combinations of sampling times may be utilized. One possible advantage to multiple and/or offset sampling timing is that samples may capture different portions of the imperfect signal eye and accuracy in determining the signal value of S1 in the presence of noise may be improved.

FIG. 59-5A1

FIG. 59-5A1 shows a memory system that uses all die in a multiple die stack for driving a memory bus (in FIG. 59-5A1), in accordance with another embodiment. As an option, the system of FIG. 59-5A1 may be implemented in the context of the architecture and environment of the previous Figures and/or any subsequent Figure(s). Of course, however, the system of FIG. 59-5A1 may be implemented in the context of any desired environment.

As shown in FIG. 59-5A1, a CPU (in FIG. 59-5A1) may be coupled to a multiple die stack utilizing a multidrop memory bus. In one embodiment, one die 59-5A1-D1 in the multiple die stack may be the designated driver (in FIG. 59-5A1). In one embodiment, the designated driver may be responsible for driving a signal 59-5A1-S2 from die 59-5A1-D1 onto the upstream memory bus to the CPU.

In one embodiment, the designated driver may be driven by a pre-driver (in FIG. 59-5A1). Additionally, in one embodiment, the designated driver may be on the same die as the pre-driver. Further, the remainder of the die (59-5A1-D2, 59-5A1-D3, 59-5A1-D4) in the multiple die stack may contain helper drivers (in FIG. 59-5A1). In one embodiment, the helper drivers may be on different die than the pre-driver. In the system of FIG. 59-5A, the pre-driver is coupled to the inputs of the helper drivers (e.g. by TSVs, etc.).

In one embodiment, the outputs of the helper drivers may be coupled to the output of the designated driver (e.g. by TSVs, etc.) and to the memory bus. Additionally, in one embodiment, the designated driver and helper drivers may cooperate to drive the memory bus.

Although FIG. 59-5A1 shows the designated driver on die 59-5A1-D1, in another embodiment, a target receiver may be located on any die within the stack depending on the origin of signal 59-5A1-S2 (e.g. the signal origin could be on die 59-5A1-D1, 59-5A1-D2, 59-5A1-D3, or 59-5A1-D4, etc.).

The extra connectivity present between die as a result of using TSVs allows the driver to spread out over multiple die. Furthermore, the use the TSVs for communication between drivers allows the drivers to cooperate. Accordingly, a stack of four die may only require a quarter of the area on each die for the driver. Additionally, the die may be spread apart physically, so a physically distributed driver may be attained, which may be useful to improve signal integrity on the bus. Although four die are illustrated in FIG. 59-5A1, any number of die may be utilized.

FIG. 59-5A2

FIG. 59-5A2 shows a die system comprising a plurality of receivers (D1A1, D1A2, D1A3, D2A1, D2A2, D2A3, D3A1, D3A2, D3A3, D4A1, D4A2, D4A3), in accordance with another embodiment. As an option, the system of FIG. 59-5A2 may be implemented in the context of the architecture and environment of the previous Figures and/or any subsequent Figure(s). Of course, however, the system of FIG. 59-5A2 may be implemented in the context of any desired environment.

FIG. 59-5A2 shows one embodiment illustrating how the die is selected using a chip select (CS) signal. In one embodiment, this will allow each die to determine whether it a designated driver or an helper driver. FIG. 59-5A2 also shows diagrammatically the utilization of the same TSV pattern and RDL as interposers between die (e.g. as a cost saving technique, etc.).

FIG. 59-5A3

FIG. 59-5A3 shows a die system, in accordance with another embodiment. As an option, the system of FIG. 59-5A3 may be implemented in the context of the architecture and environment of the previous Figures and/or any subsequent Figure(s). Of course, however, the system of FIG. 59-5A3 may be implemented in the context of any desired environment.

As shown in FIG. 59-5A3, one die may always be the designated driver and signals may be routed to the designated driver. In one embodiment, 59-5A3-D1A1 on die 59-5A3-D1 may be the designated driver and may drive signal S2 to the ball of the package. Further, driver 59-5A3-D2A1 on die 59-5A3-D2 may be selected as the pre-driver by 59-5A3-CS2 (59-5A3-CS2 has closed the switch on 59-5A3-D2). Additionally, as shown, driver 59-5A3-D3A1 on die 59-5A3-D3 may be disconnected by 59-5A3-CS3 (59-5A3-CS3 has opened the switch on 59-5A3-D3).

In another embodiment, there may be multiple other drivers connected by TSV1 (in FIG. 59-5A3).

FIG. 59-5A4-1

FIG. 59-5A4-1 shows a method 59-5A4-1-500 for controlling a configurable aspect of an electrical configuration associated with one or more circuits, in accordance with another embodiment. As an option, the method 59-5A4-1-500 of FIG. 59-5A4-1 may be implemented in the context of the architecture and environment of the previous Figures and/or any subsequent Figure(s). Of course, however, the method 59-5A4-1-500 of FIG. 59-5A4-1 may be implemented in the context of any desired environment.

As shown, a first circuit in a first physical location on a first electrical path relative to a second circuit is identified. See operation 59-5A4-1-502. Additionally, at least one configurable aspect of the first electrical path relative to the second circuit is identified. See operation 59-5A4-1-504. Further, the configurable aspect of the first electrical path relative to the second circuit is electronically controlled such that the first circuit in the first physical location is on a second electrical path relative to a second circuit. In this way, electrically controlling the first electrical path relative to the second circuit may cause the first circuit to function as if being in a second physical location relative to the second circuit.

For example, in one embodiment, the first circuit may include a driver. In this case, electrical controlling of the first electrical path relative to the second circuit may cause the driver to function as if being in a second physical location relative to the second circuit. In another embodiment, the first circuit may include a receiver. In this case, electrical controlling of the first electrical path relative to the second circuit may cause the receiver to function as if being in a second physical location relative to the second circuit.

In yet another embodiment, the first circuit may include a termination circuit. In this case, electrically controlling of the first electrical path relative to the second circuit may cause the termination circuit to function as if being in a second physical location relative to the second circuit. In either case, electrically controlling of the first electrical path relative to the second circuit may optimize a receiver channel associated with at least one of the first circuit or the second circuit.

In one embodiment, at least one property of the channel may be characterized during normal operation of a channel. In the context of the present description, normal operation of the channel refers to operation of the channel in normal operation mode. For example, in various embodiments, the normal operation may include at least one of a start-up operation, an initialization operation, a periodic calibration event, a refresh event, read commands/events, write command/events, other commands/operations (e.g. precharge, activate, mode register commands, etc.), or a power-down period.

In one embodiment normal operation may be paused while characterization is performed. In another embodiment characterization may be performed while the memory system is idle (but possibly in normal operation mode). In another embodiment characterization may be performed as part of initialization and/or start-up. In another embodiment characterization may be performed as part of calibration events (e.g. long or short calibration events, ODT calibration, or other calibration, etc.). In another embodiment characterization may be performed on detection or initiation of one or more significant system event(s) (e.g. crossing one or more system temperature thresholds, change in system voltage(s), change in other monitored system parameter(s), etc.).

In one embodiment, at least one aspect of the channel may be changed based on the characterization. For example, in one embodiment, the channel may include termination circuitry. In this case, the changing may include changing a configuration of the termination circuitry.

In another embodiment, the channel may include at least one bus. In this case, the changing may include changing a configuration of the at least one bus. In yet another embodiment, the changing may include changing an equalization associated with the channel. In another embodiment, the changing may include changing bit patterns associated with the coding.

More illustrative information will now be set forth regarding various optional architectures and features with which the foregoing techniques discussed in the context of any of the present or previous figure(s) may or may not be implemented, per the desires of the user. For instance, various optional examples and/or options associated with the identifying of operation 59-5A4-1-502, the identifying of operation 59-5A4-1-504, and the controlling of operation 59-5A4-1-506, and/or other optional features have been and will be set forth in the context of a variety of possible embodiments. It should be strongly noted, however, that such information is set forth for illustrative purposes and should not be construed as limiting in any manner. Any of such features may be optionally incorporated with or without the inclusion of other features described.

FIG. 59-5A4-2

FIG. 59-5A4-2 shows a die system, in accordance with another embodiment. As an option, the system of FIG. 59-5A4-2 may be implemented in the context of the architecture and environment of the previous Figures and/or any subsequent Figure(s). Of course, however, the system of FIG. 59-5A4-2 may be implemented in the context of any desired environment.

As shown in FIG. 5A4-2, the system may present much flexibility using switches to control connection of pre-drivers and drivers. In one embodiment, a subset of die in the multiple die stack may be helper drivers. Further, as shown in FIG. 59-5A4-2, 59-5A4-2-D2A2 and 59-5A4-2-D3A2 may both be selected as designated drivers. Thus, the designated driver is not necessarily on the same die as the pre-driver. Accordingly, the distinction between designated driver and helper driver has disappeared.

In FIG. 59-5A4-2 59-5A4-2-D1A1 is selected as the pre-driver for signal D1S1 (in FIG. 59-5A4-2).

In one embodiment, more than one pre-driver may be selected by adding additional switches and TSVs. Thus, not all pre-drivers necessarily need to be on the same die as the die that originates the signal to be driven. Additionally, in other embodiments, different numbers of pre-drivers and designated drivers may be used in permutations and combinations.

In one embodiment, a control device and memory device may be included with the pre-drivers and/or drivers. In this case, the control device may alter electrical configuration and electrical properties of the driver (e.g. a number of transistors used, an electrical drive strength, a circuit topology, timing, etc.).

In this way, signal integrity and power distribution may be improved because: (1) the driving function is spread out, which may improve the quality of the signal on the transmission line; (2) more flexibility may be realized to match the drivers and their strengths and physical locations to the transmission lines involved; (3) high current power peaks that are caused when the drivers switch may be spread (electrically and/or physically); (4) flexibility to adjust the timing of the various drivers as well as their strengths may be realized; (5) the ability to use some of the driver circuits in a very flexible way to adjust both electrical and physical location properties in combination is realized; and (6) flexibility in using the drivers for back termination (while driving) may be realized, as well as active termination on the bidirectional buses (for receiving).

As shown in FIG. 59-5A4-2, the distributed physical nature of the transistors over several die coupled by TSVs may be utilized to add elements of control to the driver and receivers on a transmission line. In this way, the physical position of transistors on a transmission line may be effectively and flexibly controlled (e.g. by switching some in and switching some out, altering topology, etc.). This technique and method may be utilized for controlling, adjusting, and improving the signal integrity on a transmission line.

In another embodiment, a variable number of helper drivers may be used (e.g. depending on the drive strength required, signal integrity of the memory bus, power restrictions, etc.). Furthermore, the number of drivers and/or pre-drivers (e.g. driver configuration) may be varied within a switching time, adjusting the properties during a signal-switching event for example. Additionally, the driver configuration may be varied with calibration events, as well as process voltage temperature (PVT) changes, etc. In various embodiments, the driver configuration may be varied because of other events, signal activity, known bad signal combinations, other activity in the system, memory system, or memory subsystem causing interferences (e.g. refresh, calibration, initialization, power-down, mode switching, etc.).

In one embodiment, driver configuration control may be autonomous (e.g. locally to a die, a package, a DIMM, the memory subsystem, etc.) or may be controlled by a CPU and/or memory controller (e.g. through configuration, at start-up, at initialization, during periodic calibration events, during refresh events, during normal operation, during power-down periods, by software, by OS, etc.). Furthermore, in one embodiment, receiver configuration may be altered in the same manner.

In one embodiment, both receiver configuration and driver configuration may be controlled independently (i.e. receiver configuration control may be separate from driver configuration control, etc.), or controlled in ways that use the combination of receiver and driver circuits together. For example, unused portions of a large driver circuit may be used for termination. In this way, using configuration control, the correct termination value(s) may be carefully placed in the correct physical and electrical location(s).

FIG. 59-5A5

FIG. 59-5A5 shows a die system, in accordance with another embodiment. As an option, the system of FIG. 59-5A5 may be implemented in the context of the architecture and environment of the previous Figures and/or any subsequent Figure(s). Of course, however, the system of FIG. 59-5A5 may be implemented in the context of any desired environment.

As shown in FIG. 59-5A5, one or more designated drivers may be used for active back termination of memory bus transmission line. In the current embodiment, switch D2Sw1 is closed enabling the driver on 59-5A5-D2 to drive signal S2 (in FIG. 59-5A5). Additionally, switch D1Sw2 is closed, enabling D1R to terminate the transmission line.

In other embodiments, more than one resistor or die may be used for termination. Furthermore, in other embodiments, the resistors may be different values. In other embodiments the termination device may be an active device or devices, combinations of resistors with active devices(s), etc. Additionally, in other embodiments, the resistors may be part of the driver circuits rather than separate as shown in FIG. 59-5A5.

In other embodiments the techniques described may be used for other functions than active back termination.

FIG. 59-5A6

FIG. 59-5A6 shows a die system, in accordance with another embodiment. As an option, the system of FIG. 59-5A6 may be implemented in the context of the architecture and environment of the previous Figures and/or any subsequent Figure(s). Of course, however, the system of FIG. 59-5A6 may be implemented in the context of any desired environment.

As shown in FIG. 59-5A6, in one embodiment, the timing of designated drivers and/or helper drivers may be adjusted (e.g. to control the slew rate of the output, to perform a staggered output to meet power restrictions, etc.).

In one embodiment, signal S1 (in FIG. 59-5A6) may switch at time t1 (in FIG. 59-5A6). Furthermore, 59-5A6-D1A1 may be programmed by D1X to switch at time t3 (e.g. similarly 59-5A6-D2A1 at t5, 59-5A6-D3A1 at t7, 59-5A6-D4A1 at t9, etc.). In this case, the result is that the positive slew rate of signal S2 (in FIG. 59-5A6) may be controlled (e.g. at time points t11, t12, t13, t14, etc.) by adjusting t3, t5, t7, t9, which in turn may be controlled by adjusting D1X, D2X, D3X, D4X.

Furthermore, as shown, signal S1 may switch at time t2 (in FIG. 59-5A6). In one embodiment, 59-5A6-D1A1 may be programmed by D1X to switch at time t4 (in FIG. 59-5A6) (e.g. similarly 59-5A6-D2A1 at t6, 59-5A6-D3A1 at t8, 59-5A6-D4A1 at t10, etc.). In one embodiment, the relative timing of D1X-D4X may be different for the positive slew rate of S1 and for the negative slew rate of S1.

Additionally, in one embodiment, signals D1X-D4X for drivers 59-5A6-D1A1, 59-5A6-D2A1, 59-5A6-D3A1, 59-5A6-D4A1 may be provided by control box(es) (e.g. using a control box similar to the control box X1 used for receivers as shown in FIG. 59-4A2, etc.). Some advantages of this technique of slew-rate control include: (1) improved signal integrity on the transmission line of the memory bus; and (2) improved control over power spikes that may cause interference and signal quality issues.

FIG. 59-6A1

FIG. 59-6A1 shows method 59-6A1-600 for applying coding to a subset of the code words, in accordance with another embodiment. As an option, the method 59-6A1-600 of FIG. 59-6A1 may be implemented in the context of the architecture and environment of the previous Figures and/or any subsequent Figure(s). Of course, however, the method 59-6A1-600 of FIG. 59-6A1 may be implemented in the context of any desired environment.

As shown, a plurality of code words are identified. See operation 59-6A1-602. Additionally, coding is applied to a subset of the code words. See operation 59-6A1-604.

The code words (e.g. codewords, bit patterns, words, signals, symbols, messages, information, data, etc.) may include any group or pattern of bits or words. In one embodiment, the code words may include one or more bit patterns. Additionally, in one embodiment, the one or more bit patterns may be identified upon receipt thereof by a receiver of a memory channel. In another embodiment, the one or more bit patterns may be identified upon receipt thereof by a driver of a memory channel and the coding may be applied prior to a transmission thereof by the driver.

The coding may include any type of coding capable of being applied to code words, and/or bit patterns, and/or sequences of bit patterns, etc. For example, in one embodiment, the coding may include an inversion algorithm. In the context of the present description, an inversion algorithm refers to any algorithm capable of being used to invert words or bits or to indicate which words or bits should be inverted. For example, in one embodiment, extra bits may be used as masks. In one embodiment, the masks may instruct the receiver which groups of data bits or code words should be inverted.

In one embodiment, the coding may include intermediate coding. Additionally, in one embodiment, applying the coding may include determining whether the second bit pattern is one of a plurality of predetermined bit patterns; and if the second bit pattern is one of the plurality of predetermined bit patterns, changing the first bit pattern to the second bit pattern in a first number of steps. In another embodiment, applying the coding may further include changing the first bit pattern to the second bit pattern in a second number of steps if the second bit pattern is not one of the plurality of predetermined bit patterns. In various embodiments, the second number of steps may include any number of steps including one step, two steps, three steps, four steps, etc.

In various embodiments, the coding may be applied to one or more subsets of the code words. In one embodiment, the coding may be applied to the subset of the code words and may not be applied to a portion of the code words not included in the subset. In this case, in one embodiment, the subset of the code words may have a first negative effect on a signal integrity and the portion of the code words not included in the subset may have a second negative effect on the signal integrity that is greater than the first negative effect on the signal integrity.

As an option, the subset of the code words may be identified utilizing at least one additional bit which control whether the coding is applied. As another option, the subset of the code words may be identified utilizing a plurality of mask bits which control whether the coding is applied.

In various embodiments, the coding may be applied to a single bus or to a plurality of buses. Furthermore, in one embodiment, the coding may be applied in connection with a transition from a first bit pattern to a second bit pattern. In this case, as an option, the coding may include causing the transition to occur with an increased number of steps. Additionally, in one embodiment, the coding may include causing the transition of a first subset of bits during a first step and the transition of a second subset of bits during a second step subsequent to the first step. In the context of the present description, a transition from one pattern to another bit pattern refers to any process of changing from one bit pattern to another bit pattern in any number of transitional steps.

In another embodiment, the method 59-6A1-600 may include causing transmission of a signal for indicating that the transition of the first subset of bits during the first step results in an incomplete bit pattern. In yet another embodiment, the method 59-6A1-600 may include causing transmission of a signal for indicating that the transition of the first subset of bits during the first step will be followed by the transition of the second subset of bits during the second step subsequent to the first step. In some cases, the coding may include causing the transition to occur with an increased duration.

More illustrative information will now be set forth regarding various optional architectures and features with which the foregoing techniques discussed in the context of any of the present or previous figure(s) may or may not be implemented, per the desires of the user. For instance, various optional examples and/or options associated with the identifying of operation 59-6A1-602, and the application of coding of operation 59-6A1-604, and/or other optional features have been and will be set forth in the context of a variety of possible embodiments. It should be strongly noted, however, that such information is set forth for illustrative purposes and should not be construed as limiting in any manner. Any of such features may be optionally incorporated with or without the inclusion of other features described.

FIG. 59-6A2

FIG. 59-6A2 shows a coding implementation for a memory channel, in accordance with another embodiment. As an option, the coding implementation of FIG. 59-6A2 may be viewed in the context of the architecture and environment of the previous Figures and/or any subsequent Figure(s). Of course, however, the coding implementation of FIG. 59-6A2 may be viewed in the context of any desired environment.

Certain combinations of data, bit patterns, etc. on a bus may present problems with signal integrity. As an example, it is assumed that there is an n-bit bus S with n signals S[0] through S[n−1] or S[0: n−1]. First focus on an individual signal on the bus, S[i]. The 20% (or some other bit pattern threshold, TBPi) of bit patterns (e.g. codewords, symbols, words, data, information, etc.) that cause the most problems in signal reception for signal S[i] may be referred to as a set of bad bit patterns for signal S[i]. The remaining 80% (assuming TBPi=0.2 then 1−TBPi=0.8) of bit patterns may be referred to as a set of good bit patterns for signal S[i].

The bit pattern that causes the greatest signal integrity problem according to a signal integrity metric SIMi (e.g. measured by the highest bit error rate (BER), highest coupled noise, worst timing margin, worst signal eye opening, etc.) is the worst-case bit pattern.

In order to characterize the bus, a threshold for the number of bad bit patterns may be set, TBP. Alternatively, a threshold for the overall bus signal integrity metric may be set, SIM. A combination of TBP and SIM may also be used.

Suppose the jth worst-case bit pattern W for signal S[i] is Wi,j. Thus the worst-case bit pattern for signal S[2] is W2,0. The next to worst-case bit pattern is W2,1 etc. The worst-case bit patterns form a set {Wi} (e.g. collection, group, etc.) of the worst-case bit patterns for signal S[i] (for some bit pattern threshold TBPi and/or signal integrity metric SIMi). Thus the set of worst-case bit patterns for S[2] would be {W2} etc. The good bit patterns for S[i] form a set {Gi}. If all possible bit patterns on bus S form set {A}, then {A}={Wi}+{Gi}.

If the analysis is repeated for all n bits on the bus, i.e. all signals, there will be some overlap between worst-case signals i.e. some bit patterns will be worst-case bit patterns for more than one signal. A set of bad bit patterns may be formed for the whole bus {B} from the sets of worst-case bit patterns for each signal {Wi}. A set bad bit patterns {B} and a set of good bit patterns {G} is then existing for the bus S, and {A}={G}+{B}.

The process of finding {B} may be illustrated with a simple example. In engineering a bus, a worst-case analysis may be performed a selection made of, for example, 25% of all bit patterns (corresponding to setting TBP=0.25) as bad bit patterns. Suppose a 4-bit bus with 2^4=16 possible bit patterns (thus {A}=0000−1111) and four signals S[0], S[1], S[2], S[3]. A threshold TBP=4/16 or 25% for this bus may be set. A timing margin analysis may be performed (by simulation, measurement, calculation etc.) and the timing margins are reported in picoseconds (ps), where a negative number represent a possible fail. After analysis we find the following six worst-case bit patterns that form {W}: (1) W0,0=0001 for S[0] (with timing margin of −25 ps), (2) W0,1=0011 for S[0] (−20 ps), (3) W1,0=0001 for S[1] (−10 ps), (4) W1,1=0011 for S[1] (−10 ps), (5) W1,2=0111 for S[1] (+50 ps), (6) W2,0=1111 for S[2] (+100 ps). Note that bit patterns 0001 and 0011 are worst-case bit patterns for two signals. Thus there are four distinct worst-case bit patterns. Thus the set {B} of four bad bit patterns for bus S (for TBP=4/16 or 25%) is {0001, 0011, 0111 1111}. The 12 remaining bit patterns out of all 16 possible bit patterns (12=16−4) form the set {G}.

In another situation we might choose the timing margin for the bus as the most important engineering criterion. A timing margin typically refers to the amount of spare or slack time available before operation of the system (e.g. bus etc.) fails or becomes marginal. If we chose our signal integrity metric SIM such that the acceptable timing margin is 0 ps for bus S, then {B}={0001, 0011} in our simple example. In other situations there may be a compromise between the number of bad bit patterns that can be handled and the signal integrity (or other metric) required and thus a combination of the approaches and methods described above may be implemented.

Once we recognize that the bad bit patterns {B} largely determine the performance of a bus and we have identified the bad bit patterns {B}, we can handle these bad bit patterns {B} in a different way than the remaining good bit patterns {G}.

The worst-case bit patterns are those bit patterns mainly responsible for reduction in signal eye opening. Therefore, in some embodiments, extra bits are used as masks. The masks may instruct the receiver(s) which groups of bits in a bit pattern should be inverted. This masked inversion is an improvement over inverting the whole bus or whole sections of the bus. The masks and bit patterns shown in FIG. 59-6A2 are exemplary.

In one embodiment, a bit pattern of 00111111 may be sent on an 8-bit bus. As an example, suppose the current value (bit pattern) on the bus is 00001110 (a bit pattern with bit 0 through bit 7 corresponding to the eight signals on a bus). If a bit pattern of 00111111 is next to be sent, then three bits (bits 2, 3, 7) corresponding to three signals would have to be flipped (e.g. inverted, changed, etc.). In addition, bit pattern 00111111 may be one of the worst-case bit patterns (e.g. a member of the bad bit pattern set) that determines the signal eye opening for one of the signals on the bus. Instead, a bit pattern of 00001111 may be sent (e.g. which is assumed not to be a bad bit pattern) with some extra information to indicate to the receiver(s) an action to be performed. In embodiment illustrated in 59-6A2, only one bit has to be flipped (bit 7). The extra information is encoded in two bits: mask bit #1, mask bit #2. In FIG. 59-6A2, a mask of 01 tells the receiver to flip bit 2 and bit 3.

As implemented, 20% of all the bit patterns possible on the signal lines on a bus may cause 80% of the eye reduction on a signal line on that bus. Put another way, if the bad bit patterns (e.g. for a given TBP and/or SIM, etc.) are eliminated, which may correspond to only 20% of all possible bit patterns, the eye opening may be increased by 80%.

In one embodiment, the j worst-case bit patterns for a given signal S[i] on bus S may be defined as those bit patterns on bus S that lead to the j highest bit-error rates (BER). These j worst-case bit patterns would then closely correspond to the j lines in the eye diagram closest to the eye inner boundary opening.

In various embodiments, the bus using masked inversion may be any width. Furthermore, in various embodiments masked inversion may be applied across more than one bus. Still yet, in various embodiments, the number of mask bits may be at any level of granularity. Thus, for example, a 64-bit bus may use 2 mask bits, or 3 mask bits etc.

FIG. 59-6B1

FIG. 59-6B1 shows a coding implementation for a memory channel, in accordance with another embodiment. As an option, the coding implementation of FIG. 59-6B1 may be implemented in the context of the architecture and environment of the previous Figures and/or any subsequent Figure(s). Of course, however, the coding implementation of FIG. 59-6B1 may be implemented in the context of any desired environment.

In FIG. 59-6B1 a 3-bit bus may be coded using normal coding that is a 1:1 mapping. Thus eight unencoded codewords, 000 to 111, map 1:1 to eight coded codewords depending on the coding scheme.

In FIG. 59-6B1, a partial coding scheme maps a subset of the unencoded codewords. For example two codewords 011 and 101 are encoded but the remaining six codewords are not. Codeword 011 maps to bit pattern sequence (010, 011), i.e. a sequence of bit patterns in time: 010 followed by 011. Codeword 101 maps to a bit pattern sequence (100, 101). Codeword 011 and 101 may otherwise correspond to bit patterns 011 and 101 that are known to cause signal interference for example. For example, assume that the two bit patterns (011 and 101) are bad bit patterns that cause signal integrity problems (the remaining six codewords correspond to good bit patterns). Thus the two codewords 011 and 101 might be sent as a sequence and the remaining six codewords are sent unencoded. (Note that we have distinguished between codewords and bit patterns here because some codewords correspond to their bit patterns when sent but some codewords are now encoded as one or more bit patterns).

The partial coding scheme of FIG. 59-6B1 and other similar partial coding schemes may help improve signal transmission in a system where not all signals, codewords, and/or bit patterns have the same signal integrity properties.

FIG. 59-6B1 shows that (binary) codewords are normally transmitted as their (digital) bit patterns but that does not need to be the case. Codewords may be mapped to symbols which may in turn be mapped to digital bit patterns or analog signals for example. The same basic idea of partial coding, i.e. coding subsets of codewords differently, applies equally however codewords are mapped or used.

Another way of looking at partial coding is that we apply more than one coding algorithm to a set of codewords.

Yet another way of looking at partial encoding is to realize that normally encoding is symmetric or uniform in that the same function, algorithm, mapping etc. is applied to all codewords. In partial coding this is not the case and codewords are handled in an asymmetric or non-uniform fashion, with subset(s) of codewords being handled differently.

Note that the masked inversion applied to a subset of codewords, as described for example in FIG. 59-6A2, may also be regarded as a form of partial coding.

In other partial coding schemes subsets of codewords may be mapped differently (e.g. using different mapping functions, etc.).

In other partial coding schemes some subsets of codewords may be mapped and some subsets of codewords not mapped. In other partial coding schemes some subsets of codewords may be mapped to a sequence (e.g. in time, etc.) or a collection (e.g. a group, set, etc.) of bit patterns or more than one sequence, group, set etc. of bit patterns.

In other partial coding schemes one or more codewords (e.g. set(s), subset(s), group(s), etc.) may be mapped to different code(s) (e.g. symbol(s), bit pattern(s), etc.) that are then mapped again (e.g. nested mapping, etc.).

In other partial coding schemes one or more codewords may be mapped using a different (e.g. not unique, variable, etc.) mapping depending on state, time or other factors (e.g. noise in the system, power constraints, etc.).

In other partial coding schemes one or more sequences of codewords may also be mapped according to any of the schemes and variations described.

FIG. 59-6B2

FIG. 59-6B2 shows a coding implementation for a memory channel, in accordance with another embodiment. As an option, the coding implementation of FIG. 59-6B2 may be viewed in the context of the architecture and environment of the previous Figures and/or any subsequent Figure(s). Of course, however, the coding implementation of FIG. 59-6B2 may be viewed in the context of any desired environment.

As shown in 59-6B2, 010 and 011 are both good bit patterns (i.e. are not bad bit patterns). In some cases, it is easier to determine (e.g. by simulation or by calculation, etc.) the bad bit patterns than it is to determine the good bit patterns. For example, on a bus with 64 bits, at least 2^64*2^64 simulations may have to be made, which may be a prohibitively large number.

In one embodiment, instead of sending signals (e.g. bit patterns, symbols, codewords, data, sequences of signals, etc.) on a memory bus that may require a change of many bits at once, one or more intermediate steps may be taken in which only some of the bits are changed at a time at each intermediate step(s). This form of partial coding may be referred to as intermediate coding. One feature of intermediate coding is that the intermediate step(s) may be taken for only some (e.g. a set, a subset, a group, etc.) of all possible codewords (e.g. signals, information, data, bit patterns, symbols, sequence(s) of codewords, etc.) that may be sent on the bus.

In one embodiment, the intermediate coding may be applied only to a subset of p code words on bus S that correspond to worst-case bit patterns. In some cases, p may be made up of m1 worst-case bit patterns determined from the BER statistics or eye diagram for S[1], plus m2 worst-case bit patterns from S[2], etc. In this case, m1, m2 etc. are generally not equal.

In another embodiment, a threshold TBER for the overall BER on bus S may be made and all those bit patterns that cause a BER greater than TBER will be subject to intermediate coding. In one embodiment, when an intermediate code is sent, a wait (e.g. hang on, more to come, etc.) signal may also be sent so the receiver knows that the intermediate code is not the final signal.

In various embodiments, the wait bit may be an extra bit added to the bus, a re-purposed control or command bit that is available (i.e. not required, not otherwise used, can be shifted in time, etc.) at the required time slot, an address bit or special pattern (e.g. if the address bus, or part of the address bus, is not being used at the required time slot, etc.), or a data bit (or special pattern) if the data bus, or part of the data bus, is not being used at the required time slot. It should be noted that the bit patterns shown in FIG. 59-6B2 are exemplary. In one embodiment, intermediate coding may be used with any other form of coding [e.g. error correcting codes (ECC), cyclic redundancy check (CRC) codes, line codes (e.g. 8B10B etc.), trellis codes, block codes, data bus inversion (DBI), masked inversion (as previously described), etc.] or combination(s) of coding schemes (e.g. other partial coding schemes, other encoding schemes, mappings, etc.).

In various embodiments, intermediate coding used in combination with other code(s) may be applied in any order (e.g. as an inner, outer or intermediate code, etc.) or in any combined fashion (e.g. convolved, punctuated, continuous, overlapped, non-overlapped, etc.). In one embodiment, intermediate coding may be applied to parts of the bus (e.g. to only the 8 worst bits on a 64-bit bus, etc.). Additionally, in one embodiment, intermediate coding may be applied across the whole bus (e.g. across all 64 bits on a 64-bit bus).

In yet another embodiment, intermediate coding may be applied separately across parts of the bus (e.g. on a 64-bit bus you could use an intermediate coding scheme 1 for bits 0-10, intermediate coding scheme 2 for bits 11-15, no coding for bits 16-63, etc.). In one embodiment, this may be implemented to aid the computation required to calculate when and how to use intermediate codes.

Reducing the size of a bus significantly helps in calculating the bad bit patterns. Thus, for example, it may be much easier to calculate the bad bit patterns for two 32-bit buses than it is for one 64-bit bus. In certain embodiments it may also be preferable to physically separate or otherwise treat a large bus as one or more smaller buses. For example a 64-bit bus may be routed on two layers of a PCB, with one layer carry 32 bits and another layer the remaining 32 bits. Interference between the two 32-bit buses may be minimized by such layer separation and thus the two buses may then be treated separately for the calculation of bad bit patterns. Thus the two 32-bit buses may use their own, separate, partial coding schemes, for example.

As described, in some embodiments, it may be advantageous to use intermediate coding, possibly with other codes, to eliminate the worst-case bit patterns and sequences because in high-speed channels not all bit patterns and sequences are necessarily equal in their signal integrity properties. For the same reason, in some embodiments, it may be advantageous to use codes used in combination with other code(s) on separate parts of a bus (e.g. coding scheme 1 used on bits 0-31 and coding scheme 2 used on bits 32-64, etc.).

In one embodiment, codes used in combination with other code(s) may be also be used on overlapping parts of a bus in overlap coding. For example in one overlap coding scheme for a 64-bit bus, a coding scheme 1 is used on bits 0-47 and coding scheme 2 is used on bits 32-64. In these embodiments one or more of coding scheme 1 and coding scheme 2 may be partial coding schemes, but do not have to be. In these embodiments overlap(s) may occur but do not have to be present. Of course more than two coding schemes may also be used.

FIG. 59-6B3

FIG. 59-6B3 shows a coding implementation for a memory channel, in accordance with another embodiment. As an option, the coding implementation of FIG. 59-6B3 may be viewed in the context of the architecture and environment of the previous Figures and/or any subsequent Figure(s). Of course, however, the coding implementation of FIG. 59-6B3 may be viewed in the context of any desired environment.

FIG. 59-6B3 shows the effect of using intermediate coding is to avoid sending worst-case bit patterns that correspond to a smaller signal eye opening, in accordance with one embodiment. Thus without intermediate coding we might get the eye inner boundary #2, but with intermediate coding we get the better (e.g. wider, more open, cleaner, etc.) eye inner boundary #1.

FIG. 59-6B3 shows how a sequence of transmitted digital binary bits (1 or 0) that form a sequence of bits in time separated by the clock period is received, on a transmission line for example, as overlapping analog waveforms. In FIG. 59-6B3, the received analog waveform for each bit is superimposed (one on top of another) and shows for any given clock period what the received waveforms could look like. FIG. 59-6B3 is called an eye diagram (e.g. signal eye, received eye, etc.).

In FIG. 59-6B3 the eye signal outer boundary represents the largest analog waveform amplitudes received. In FIG. 59-6B3 the eye #2 inner boundary represents smallest signal amplitudes received. In general the smallest signal amplitudes received correspond to the worst-case bit patterns. In FIG. 59-6B3 if we were to remove the worst-case bit patterns that for example represented 20% of all possible bit patterns the signal eye inner boundary may change to eye #1 inner boundary. The resultant change corresponds to an opening of the signal eye corresponding to better signal integrity and improved signal reception.

FIG. 59-7A

FIG. 59-7A shows a memory system including a DIMM on a chip (in FIG. 59-7A), in accordance with another embodiment. As an option, the memory system of FIG. 59-7A may be implemented in the context of the architecture and environment of the previous Figures and/or any subsequent Figure(s). Of course, however, the memory system of FIG. 59-7A may be implemented in the context of any desired environment.

As shown, in one embodiment, the DIMM on a chip may comprise a multiple die stack comprising four 16-bit DRAM die (59-7A-D1, 59-7A-D2, 59-7A-D3, 59-7A-D4). In one embodiment, the bottom die in the multiple die stack may be a designated DIMM die (in FIG. 59-7A). As an option, the designated DIMM die may implement designated receiver(s) and/or designated driver(s) (e.g. as described in other Figures, etc.). In one embodiment, the designated DIMM die may implement other DIMM and memory module support functions [e.g. buffer(s), buffer circuit(s), buffer chip(s), register(s), intermediate circuit(s), power supply regulation, hub(s), re-driver(s), PLL(s), DLL(s), non-volatile memory, SRAM, DRAM, logic, passive components, combinations of these and other circuits, etc.].

In another embodiment, the designated DIMM die may be coupled to a CPU (in FIG. 59-7A) by a 64-bit data bus (in FIG. 59-7A) (e.g. channel, link, etc.), a command (in FIG. 59-7A) and/or address bus, and/or a control bus (in FIG. 59-7A), etc. Further, in various embodiments, the 64-bit data bus may be bidirectional, the control bus may be bidirectional, and/or the command bus may be an address bus with or without command information. Additionally, in other embodiments there may be other buses not shown in FIG. 59-7A (e.g. a separate address bus, a multiplexed address bus, etc.). In other embodiments the buses may be of any width.

In another embodiment, the designated DIMM chip may be a different die than the rest of the die in the multiple die stack. In another embodiment, there may be more than one designated DIMM chip in the multiple die stack. In another embodiment, the designated DIMM chip may be integrated with one or more of the memory die. Further, in another embodiment, the DIMM on a chip can be any data width (e.g. 64 bits, 72 bits, 128 bits, 144 bits, 512 bits, etc.).

In one embodiment, the DIMM on a chip may contain multiple ranks. Additionally, in another embodiment, the DIMM on a chip may contain multiple memory technologies. Further, in another embodiment, the designated DIMM chip may convert from parallel bus(es) to high-speed serial bus(es) and/or change data rates, frequencies, memory protocols, bus protocols, coding schemes, decoding schemes, pre-fetch schemes, compression schemes, decompression schemes, deduplication functions, signaling schemes, logic signal functions, voltages, optical conversion, etc. In another embodiment, there may be more than one stack in a multiple die package with more than one designated DIMM chip.

Still yet, in one embodiment, the function of the designated DIMM chip may be virtual, i.e. the functions, resources, circuits, etc. required by the designated DIMM chip(s) may be physically located throughout the stack(s) but may logically appear, for example, as a separate chip or chips. Still yet, any number of die may be included in the die stack(s).

FIG. 59-7B

FIG. 59-7B shows a memory subsystem (in FIG. 59-7B) consisting of 8 multiple die stacks, coupled to a 512 bit bus (in FIG. 59-7B), in accordance with another embodiment. As an option, the memory system of FIG. 59-7B may be implemented in the context of the architecture and environment of the previous Figures and/or any subsequent Figure(s). Of course, however, the memory system of FIG. 59-7B may be implemented in the context of any desired environment.

In FIG. 59-7B each of the eight multiple die stacks contributes 64 bits to the data bus.

In different embodiments the data bus may be any width.

In different embodiments there may be one or more intermediate circuit(s) that may convert the data bus width presented by the multiple die stacks to the data bus width of the memory bus coupled to the CPU(s) (in FIG. 59-7B). For example the multiple die stacks may present a 512-bit data bus to an intermediate circuit that converts the data bus with to 64 bits. In different embodiments the intermediate circuit(s) may be part of one or more multiple die stack(s), integrated with one or more of the memory circuits, separately packaged, etc. In different embodiments the intermediate circuit(s) may perform a serial-to-parallel or parallel-to-serial conversion possibly also performing a change in data bus width, bus protocol, logic function, signaling scheme, voltage level, single-end to differential, encoding/decoding etc.

FIG. 59-7C

FIG. 59-7C shows a memory subsystem (in FIG. 59-7C) with a 512-bit bus (in FIG. 59-7C) coupled to a buffer chip (in FIG. 59-7C), in accordance with another embodiment. As an option, the memory subsystem of FIG. 59-7C may be implemented in the context of the architecture and environment of the previous Figures and/or any subsequent Figure(s). Of course, however, the memory subsystem of FIG. 59-7C may be implemented in the context of any desired environment.

As shown in FIG. 59-7C, the buffer chip includes a parallel-to-serial and serial-to-parallel converter. In one embodiment, the buffer chip may allow high-speed high-bandwidth serial communication between a CPU (in FIG. 59-7C) and the memory subsystem without the need to hardwire 512 separate connections.

The throughput of Intel QuickPath Interconnect (QPI), corresponds to a 64-bit data payload in an 80-bit flit using a 20-lane QPI link pair (for send and receive) and a 3.2 GHz clock. The 80-bit flit uses 8 bits for error detection, 8 bits for the link-layer header, and 64 bits for data. Each QPI comprises two 20-lane point-to-point data links, one in each direction (full duplex), with a separate clock pair in each direction, for a total of 42 signals. Each signal is a differential pair, so the total number of pins used is 84. The 20 data lanes are divided onto four quadrants of 5 lanes each. The basic unit of transfer is the 80-bit flit, which is transferred in two clock cycles (four 20 bit transfers, two per clock). The two-link 20-lane QPI transfers eight bytes per clock cycle, four in each direction. The data rate of Intel QPI is thus as follows: 3.2 GHz (clock)×2 bits/Hz (double data rate)×20 (QPI link width)×(64/80)(data bits/flit bits)×2 (bidirectional links)/8 (bits/byte)=25.6 GB/s.

The throughput of JEDEC standard DDR3 memory module technology, offers data rates from 6.4 GBps (a PC3-6400 module using DDR3-800 SDRAM with memory clock of 100 MHz, cycle time of 10 ns, memory bus clock 400 MHz, data rate 800 MT/s) to 17.066 GBps (a PC3-17000 module using DDR3-2133 SDRAM with memory clock of 266 MHz, cycle time of 3.75 ns, memory bus clock 1066 MHz, data rate 2133 MT/s).

The throughput of JEDEC standard DDR4 SDRAM memory technology is expected (using a 28-25 nm process node) to offer data rates from 1600 Mbps (corresponding to a memory cell frequency of 100 MHz and cycle time of 10 ns) to 4266 Mbps (memory cell frequency of 266 MHz and cycle time of 3.75 ns) corresponding to memory module data rates of 6.4G Bps to 34 GBps.

It is thus possible to take a 512-bit parallel bus memory technology (e.g. DDR3, etc.) running at a 400 MHz memory bus speed that corresponds to a bandwidth of about 50 GBps and convert this to a high-speed serial bus equivalent to two QPI links using a 3.2 GHz clock.

In other embodiments, different serial link technologies may be used (e.g. HyperTransport, PCI Express, InfiniBand, high-speed USB, high-speed Ethernet, etc.). Furthermore, in one embodiment, multiple serial links may be used in parallel. Still yet, a single high-speed serial link may be used. In one embodiment, the serial link(s) may use a split transaction protocol, such as PCI Express. Further, in one embodiment, the serial link(s) may use a packet-based protocol, such as QPI or HyperTransport. Additionally, the serial link(s) may be used a routable protocol, such as TCP over high-speed Ethernet, etc.

In one embodiment, the serial link(s) may be used a high-speed physical layer protocol, such as 10 Gbps Ethernet, 40 Gbps Ethernet, etc. In another embodiment, the serial link(s) may use optical high-speed links such as Sonet, SDH, etc. In yet another embodiment, the serial link(s) may use a high-speed storage protocol such as SAS, Fibre Channel, etc. In other embodiments the serial link(s) may use combinations of protocols and bus systems may be used (e.g. USB over Ethernet, USB over PCI Express, Thunderbolt, Lightpeak, etc.). In other embodiments other forms of high-speed, high bandwidth link(s) between CPU and buffer chip(s) may be used.

FIG. 59-8A1

FIG. 59-8A1 shows a method 59-8A1-800 for changing at least one aspect of a channel based on a characterization, in accordance with another embodiment. As an option, the method 59-8A1-800 of FIG. 59-8A1 may be implemented in the context of the architecture and environment of the previous Figures and/or any subsequent Figure(s). Of course, however, the method 59-8A1-800 of FIG. 59-8A1 may be implemented in the context of any desired environment.

As shown, at least one property of a channel is characterized during normal operation of the channel. See operation 59-8A1-802. Additionally, at least one aspect of the channel is changed based on the characterization. See operation 59-8A1-804. In the context of the present description, normal operation of the channel refers to operation of the channel in normal operation mode. For example, in various embodiments, the normal operation may include at least one of a start-up operation, an initialization operation, a periodic calibration event, a refresh event, or a power-down period.

Additionally, the characterization may be implemented in a variety of ways. For example, in one embodiment, the characterizing may include sampling a signal on the channel. In another embodiment, the characterizing may include determining at least one of a power or temperature associated with a channel.

In one embodiment, characterizing the channel may include determining if the channel is capable of one or more optimizations. The optimizations may include any number of optimizations associated with the channel. Furthermore, the property of the channel that is characterized during normal operation of the channel may include a variety of channel properties. For example, in one embodiment, the at least one property may include an impulse response. In another embodiment, the at least one property may include a frequency response.

Furthermore, in one embodiment, changing the aspect of the channel may be based on the characterization includes optimizing the at least one aspect of the channel based on the characterization. In another embodiment, the changing may include iteratively optimizing the at least one aspect of the channel based on the characterization.

In various embodiments, the channel may include termination circuitry, receiver circuitry, a bus, and/or other components. In this case, changing the aspect may include changing an aspect of circuitry, etc. associated with those components.

In another embodiment, the changing may include changing an equalization associated with a transmission of the channel or a reception of the channel. Additionally, in one embodiment, the changing may include changing a coding associated with the channel. For example, in one embodiment, the changing may include changing bit patterns associated with the coding.

In any case, the changing may be capable of being implemented while the channel is in an operable physical location. For example, in one embodiment, the changing may be capable of being implemented while the channel is positioned in a computing device. The computing device may include a device capable of computing, such as a computer, a PDA, a phone, and any mobile or stationary computing device.

In various embodiments, the channel may include different configurations. For example, in one embodiment, the channel may include a first portion between at least one processor and a first semiconductor platform and a second portion between the first semiconductor platform and a second semiconductor platform. In one embodiment, the first semiconductor platform may be stacked with the second semiconductor platform. Additionally, in one embodiment, the first semiconductor platform may be adjacent to the second semiconductor platform.

In one embodiment, the characterizing of the channel may include characterizing the first portion between at least one processor and the first semiconductor platform and the second portion between the first semiconductor platform and the second semiconductor platform.

More illustrative information will now be set forth regarding various optional architectures and features with which the foregoing techniques discussed in the context of any of the present or previous Figure(s) may or may not be implemented, per the desires of the user. For instance, various optional examples and/or options associated with the characterizing of operation 59-8A1-802, and the changing of operation 59-8A1-804, and/or other optional features have been and will be set forth in the context of a variety of possible embodiments. It should be strongly noted, however, that such information is set forth for illustrative purposes and should not be construed as limiting in any manner. Any of such features may be optionally incorporated with or without the inclusion of other features described.

FIG. 59-8A2

FIG. 59-8A2 shows a system implementation for characterizing a memory system, in accordance with another embodiment. As an option, the system of FIG. 59-8A2 may be implemented in the context of the architecture and environment of the previous Figures and/or any subsequent Figure(s). Of course, however, the system of FIG. 59-8A2 may be implemented in the context of any desired environment.

As shown in FIG. 59-8A2, the CPU (in FIG. 59-8A2) may be coupled to the memory bus (in FIG. 59-8A2). Additionally, in one embodiment, the memory bus may be coupled to a DRAM package (in FIG. 59-8A2). In one embodiment, the DRAM package may include a 4 DRAM die stack (in FIG. 59-8A2).

As one exemplary implementation, a maximal length pseudo random binary sequence (PBRS) (in FIG. 59-8A2) of length 31 bits may be:

0 0 1 1 0 1 0 0 1 0 0 0 0 1 0 1 0 1 1 1 0 1 1 0 0 0 1 1 1 1 1

A substitution of analog value −1 may be made for the binary value 1 and analog value +1 for the binary value 0, resulting in the following analog sequence of values:

1 1 −1 −1 1 −1 1 1 −1 1 1 1 1 −1 1 −1 1 −1 −1 −1 1 −1 −1 1 1 1 −1 −1 −1 −1 −1

If this analog sequence is multiplied by itself (e.g. bit 0 times bit 0 plus bit 1 times bit 1 . . . plus bit 31 times bit 31, etc.), the analog result is 31.

If this analog sequence is shifted by one bit to the right in time (e.g. bit 0 becomes bit 1, bit 1 becomes bit 2, . . . , bit 31 becomes bit 0, etc.), the result is the following +1 shifted analog sequence:

−1 1 1 −1 −1 1 −1 1 1 −1 1 1 1 1 −1 1 −1 1 −1 −1 −1 1 −1 −1 1 1 1 −1 −1 −1 −1

If this +1 shifted analog sequence is multiplied with the original analog sequence, the result is −1. If this +1 shifted analog sequence is shifted by one bit again (e.g. bit 0 becomes bit 1, bit 1 becomes bit 2, . . . , bit 31 becomes bit 0, etc.), the following +2 shifted analog sequence is the result:

−1 −1 1 1 −1 −1 1 −1 1 1 −1 1 1 1 1 −1 1 −1 1 −1 −1 −1 1 −1 −1 1 1 1 −1 −1 −1

If this +2 shifted analog sequence is multiplied with the original analog sequence, −1 is the result. If this +2 shifted analog sequence is shifted by one bit again (e.g. bit 0 becomes bit 1, bit 1 becomes bit 2, . . . , bit 31 becomes bit 0, etc.), the result is the following +3 shifted analog sequence:

−1 −1 −1 1 1 −1 −1 1 −1 1 1 −1 1 1 1 1 −1 1 −1 1 −1 −1 −1 1 −1 −1 1 1 1 −1 −1

Repeating the shift and multiply process for all shifts except for zero and multiples of 32, the result of the multiplication is −1, while for zero shift the result is 31. This shift and multiply process is equivalent to finding the autocorrelation function of the PRBS.

The autocorrelation function of a PRBS is thus a periodic pulse function with value −1 and peak +31 that approximates the Dirac delta function very well. The properties of the Dirac delta function may be used to find the impulse response of a linear time-invariant (LTI) system. In one embodiment, to find the impulse response of a linear time-invariant system the following steps may be performed:

1. Transmit the PRBS of length n through the system;

2. Take the analog output and shift by m time steps, with m=1−n;

3. At each shift multiply the analog output with the PRBS; and

4. The result is the impulse response of the system, which is the Fourier transform of the frequency response.

Additionally, in one embodiment, to find the impulse response of the memory channel, the following steps may be performed:

1. Transmits a shifted PRBS delayed by n clock cycles (e.g. CPU transmits, etc.), where n=0-31 and the clock cycle is d as shown in the FIG. 59-8A2 waveform labeled A (in FIG. 59-8A2). In FIG. 59-8A the PRBS is 31 bits long (2^5-1);

2. Take the analog output as shown in the FIG. 59-8A2 waveform labeled B (in FIG. 59-8A2) and multiply by the un-shifted PRBS.

This process may be repeated 31 times, equal to the number of bits in the PRBS. The 31 results from Step 2 executed 31 times form the impulse response of the memory channel.

The analog signals may be sampled on one or more die within the multiple die stack. The impulse response of the memory channel may thus be measured for multiple physical locations.

In another embodiment, the signals may be sampled by more than one die within the multiple die stack. The impulse response may then be more accurately calculated by using multiple independent samples to eliminate noise, etc.

In other embodiments different lengths of PRBS may be used. In other embodiments different analog values for the PRBS may be used.

In various embodiments, there may be many ways to measure the channel characteristics. In one embodiment, the receiver and/or driver configuration may be altered as a result of memory channel characterization Memory channel characterization may be performed at any time (e.g. at start-up, at initialization, during periodic calibration events, during refresh events, during normal operation, during power-down periods, etc.).

In various embodiments, other techniques for characterizing the memory channel may be implemented (e.g. measuring signal integrity behavior of a channel, measuring BER, creating eye diagrams, determining frequency response, determining impulse response, etc.). Using the systems and techniques described herein, the frequency response of the memory channel may be determined in real time.

FIG. 59-9

FIG. 59-9 shows a system implementation for improving the performance of a memory channel, in accordance with another embodiment. As an option, the system of FIG. 59-9 may be implemented in the context of the architecture and environment of the previous Figures and/or any subsequent Figure(s). Of course, however, the system of FIG. 59-9 may be implemented in the context of any desired environment.

In one embodiment, a memory system may include memory modules that are arranged in slots. In one embodiment, each memory module may include a number of memory chips. For example, in one embodiment, the memory module may be a DIMM and the memory chips may be DRAM chips. In various embodiments, memory modules may be physically placed in slot connectors and may be electrically coupled to other components (e.g. one or more memory controllers, etc.) through channels and buses. These channels and buses may form transmission lines that are electrically terminated, for example, at the connected DIMMs.

In one embodiment, a memory controller may select any of the DIMMs in a channel for reading or writing, but only access one DIMM at a time. The slot in which the DIMM accessed for reading or writing is located is referred to as the active slot, while slots in which the other non-accessed DIMMs are located are referred to as the standby slots.

A DIMM may have a single rank or multiple ranks. In the context of the present description, a rank refers to an independent set of DRAMs within the DIMM that can be simultaneously accessed (typically using a chip select or other control signal(s), etc.) to access the full data bit-width of the DIMM (e.g. 72 bits, etc.). The rank to which data is being written is called the target rank for writes. The rank from which data is being read is called the target rank for reads. The ranks that are not targets are non-target ranks.

The use of designated receiver(s) for transmission line termination of the memory bus(es) allows for the creation of a single or multiple point(s) of termination for a DIMM. Proper bus termination may improve performance, reduce cost, and provide other benefits for a memory module design. In one embodiment, an interface circuit for transmission line termination can be used to tune termination value(s) for one or more DIMM(s). Standard termination values, for example the termination values mandated/recommended by Joint Electron Devices Engineering Council (JEDEC), might not always be optimal for a given DIMM, leading to sub-optimal performance.

The use of designated receiver(s) for transmission line termination can provide optimal on-die termination (ODT) resistance for a given DIMM, which improves signal integrity and minimizes noise on the transmission line(s). Furthermore, the use of the designated receiver(s) can also provide termination resistance for a DIMM that is different (e.g. higher or lower) than the resistance mandated by a standard. If a higher termination resistance is used while signal integrity is maintained, power dissipation will be reduced because the amount of dissipated power is inversely proportional to the value of termination resistance. If a lower termination resistance is used signal integrity may be improved because reflections that produce noise and interference may be reduced. As a result, the use of designated receiver(s) for transmission line termination can improve electrical performance and signal quality within a memory system using one or more DIMMs.

As shown in FIG. 59-9, the CPU (in FIG. 59-9) is coupled to a receiver on a DRAM die (in FIG. 59-9). In one embodiment, the DRAM die may be contained within a multiple die stack. As shown further, the CPU may include a driver (in FIG. 59-9). In one embodiment, the driver may be coupled to one transmission line (in FIG. 59-9). In another embodiment, the driver may be coupled to more than one transmission line. Transmission line(s) may represent any of various memory buses including those shown in previous and following Figures.

In one embodiment, the ODT resistance RX (in FIG. 59-9) may be adjustable. As shown in FIG. 59-9, RX may be adjusted. For example, RX may be tuned, varied, altered in topology (e.g. by using more than one designated receiver and/or designated driver used for termination), or moved in position through receiver or driver configuration, etc. based on various metrics (e.g. characterization of the memory channel, calculation, BER, signal integrity, etc.).

In one embodiment, a different termination value may be used for each receiver within a multiple die stack. In another embodiment, different groups of receivers may have different terminations. In another embodiment, the driver electrical characteristics of the driver(s) may be adjusted (e.g. in similar fashion to the termination resistance, etc.). In various embodiments, the driver electrical characteristics may include static and/or dynamic drive strength, DC transfer characteristics, AC small-signal transfer characteristics, drive resistance, slew rate (e.g. maximum slew rate, slew rate control, etc.), and dynamic back termination, etc.

In other embodiments termination(s) may be located at one or more location(s) (e.g. using ODT on one or more die, using termination at one or more designated die in a multi-die stack, using termination on buffer(s) or intermediate circuit(s), combinations of these, etc.).

In other embodiments termination may use a combination of termination from active and standby slots and from target and non-target ranks. For example to achieve a termination value of 50 Ohm, standby slot termination may be set to 100 Ohm in parallel with active slot termination of 100 Ohm. In other embodiments the use of target and non-target rank termination values may also be adjusted. Thus for example, to achieve an active slot termination of 100 Ohm, the target rank termination may be set to 200 Ohm in parallel with a non-target rank termination of 200 Ohm.

In other embodiments the values, behavior, topology, locations, and configuration etc. of termination(s) may be set separately for read and writes or may be dependent on other commands, memory subsystem operations, operating modes, etc.

In other embodiments the adjustment of the values, behavior, topology, locations, and configuration etc. of termination(s) may be set by the CPU, system, OS, hardware, software etc. or by the memory subsystem in an autonomous fashion.

In different embodiments the values, behavior, topology, locations, and configuration etc. of termination(s) etc. may be set at start-up, initialization etc. or changed dynamically (i.e. changed from clock cycle to clock cycle, changed within a clock cycle, changed from command to command, changed within a command, changed between calibration periods, etc.) during operation depending on system parameters such as signal integrity, error rate, power, performance required, etc.

FIG. 59-10

FIG. 59-10 shows an equalization implementation, in accordance with another embodiment. As an option, the equalization implementation of FIG. 59-10 may be implemented in the context of the architecture and environment of the previous Figures and/or any subsequent Figure(s). Of course, however, the equalization implementation of FIG. 59-10 may be implemented in the context of any desired environment.

As shown in FIG. 59-10, a binary sequence “1101” (e.g. using an analog value of 0V to represent logical binary value “0” and an analog value of 1.8V to represent logical binary value “1”) may be transmitted. In some cases, the initial sequence of two “1”s may transfer enough energy into the memory channel that energy may “spill over” from time t0-t2 into the time period t2-t3. In some cases, this energy may interfere with proper reception of a “0” between t2 and t3. In order to correct for this effect the analog value of the “1”s in time period t0-t2 may be reduced using de-emphasis (e.g. to an analog value of 1.7V) as shown in FIG. 59-10.

In contrast, the single “1” transmitted between t3 and t4 may not have enough energy to be properly received at the end of the memory channel. In order to correct for this effect, the analog value of the “1” in time period t3-t4 may be increased using emphasis (to an analog value of 1.9V) as shown in FIGS. 59-10.

In different embodiments, emphasis and/or de-emphasis may be performed at the designated driver(s) in a multiple die stack [e.g. the transmitter, driver, re-driver on a buffer etc. both for the upstream memory bus(es) or downstream memory bus(es), etc.]. Additionally, in different embodiments, emphasis and/or de-emphasis may be performed at the designated receivers(s) in a multiple die stack [e.g. the receiver(s) both for the upstream memory bus(es) or downstream memory bus(es), etc.]. Further, in different embodiments, emphasis and/or de-emphasis may be performed at the designated receivers(s) in a multiple die stack [e.g. the receiver(s) for the downstream memory bus(es), etc.] and/or at the designated driver(s) in a multiple die stack [e.g. the transmitter, driver, re-driver on a buffer etc. both for the upstream memory bus(es), etc.].

In various embodiments (e.g. including any of those embodiments mentioned previously or combinations of these embodiments, etc.), the emphasis and/or de-emphasis may be adjustable. In various embodiments, the emphasis and/or de-emphasis may be adjusted [e.g. tuned, varied, altered in function (e.g. by using more than one designated receiver and/or designated driver used for emphasis and/or de-emphasis, etc.), moved in position through receiver or driver configuration, etc.] based on various metrics (e.g. characterization of the memory channel, calculation, BER, signal integrity, etc.).

The capabilities of the present invention can be implemented in software, firmware, hardware or some combination thereof.

As one example, one or more aspects of the present invention can be included in an article of manufacture (e.g., one or more computer program products) having, for instance, computer usable media. The media has embodied therein, for instance, computer readable program code means for providing and facilitating the capabilities of the present invention. The article of manufacture can be included as a part of a computer system or sold separately.

Additionally, at least one program storage device readable by a machine, tangibly embodying at least one program of instructions executable by the machine to perform the capabilities of the present invention can be provided.

The diagrams depicted herein are just examples. There may be many variations to these diagrams or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order, or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention.

While various embodiments have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of a preferred embodiment should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. 

What is claimed is:
 1. An apparatus, comprising: a physical memory sub-system including: a first memory of a first memory class; and a second memory of a second memory class, the second memory communicatively coupled to the first memory; wherein the apparatus is configured such that the first memory and the second memory are capable of being used for a random access data read from the first memory via the second memory as a result of the physical memory sub-system receiving multiple instructions via a single memory bus, by: receiving an instruction via the single memory bus for operating on data, that results in: a first operation on at least a portion of the data in connection with the first memory, a second operation in connection with the second memory, that results in storage of the at least portion of the data in the second memory, and a status being provided; and after the status being provided, receiving another instruction via the single memory bus for operating on the at least portion of the data, that results in the at least portion of the data being read from the second memory; wherein the apparatus is configured such that the physical memory sub-system requires receipt of the multiple instructions via the single memory bus for the random access data read from the first memory via the second memory.
 2. The apparatus of claim 1, wherein the first memory class includes non-volatile memory, and the second memory class includes volatile memory.
 3. The apparatus of claim 1, wherein the communicative coupling includes a connection via a buffer device.
 4. The apparatus of claim 1, wherein the first memory class includes flash memory, and the second memory class includes dynamic random access memory.
 5. The apparatus of claim 1, wherein the apparatus is configured such that the second memory of the second memory class is capable of serving as at least one of a temporary store or a de-staging mechanism for the first memory of the first memory class.
 6. The apparatus of claim 1, wherein the apparatus is configured such that the second memory of the second memory class is capable of serving as a buffer.
 7. The apparatus of claim 1, wherein the apparatus is configured such that the single memory bus is associated with a DDR3 or DDR4 protocol.
 8. The apparatus of claim 7, wherein the apparatus is configured such that commands associated with another protocol are received via the single memory bus utilizing the DDR3 or DDR4 protocol.
 9. The apparatus of claim 7, wherein the apparatus is configured such that commands associated with a SATA protocol are received via the single memory bus utilizing the DDR3 or DDR4 protocol.
 10. The apparatus of claim 1, wherein the first memory includes NAND flash memory and the second memory includes dynamic random access memory, and the physical memory sub-system further includes: a first buffer including the second memory, the first buffer capable of being communicatively coupled to the single memory bus; and a second buffer communicatively coupled to a third memory, the second buffer communicatively coupled between the first buffer and the first memory such that the second buffer is communicatively coupled to the first buffer via a first additional memory bus and the second buffer is communicatively coupled to the first memory via a second additional memory bus.
 11. The apparatus of claim 10, wherein the apparatus is configured such that the second memory includes dynamic random access memory that is embedded dynamic random access memory.
 12. The apparatus of claim 10, wherein the apparatus is configured such that the third memory is of the second memory class.
 13. The apparatus of claim 10, wherein the apparatus is configured such that the third memory is of a third memory class.
 14. The apparatus of claim 10, wherein the apparatus is configured such that the second buffer includes the third memory.
 15. The apparatus of claim 10, wherein the apparatus is configured such that the second memory of the first buffer is capable of serving as at least one of a temporary store or a de-staging mechanism for the first memory.
 16. The apparatus of claim 10, wherein the apparatus is configured such that at least two of the first memory, the second memory, and the third memory are hierarchically coupled.
 17. The apparatus of claim 10, wherein the apparatus is configured such that the single memory bus is associated with a DDR3 or DDR4 protocol.
 18. The apparatus of claim 10, wherein the apparatus is configured such that the first additional memory bus is associated with a SATA protocol.
 19. The apparatus of claim 10, wherein the apparatus is configured such that the second additional memory bus is associated with a NAND flash protocol.
 20. The apparatus of claim 1, wherein the physical memory sub-system includes: NAND flash memory; dynamic random access memory; a first circuit for receiving DDR signals and converting the DDR signals to SATA signals, the first circuit including embedded dynamic random access memory; and a second circuit for receiving the SATA signals and converting the SATA signals to NAND flash signals, the second circuit communicatively coupled to the first circuit via a first additional memory bus associated with a SATA protocol, the second circuit further communicatively coupled to the NAND flash memory via a second additional memory bus associated with a NAND flash protocol, the second circuit further communicatively coupled to the dynamic random access memory.
 21. The apparatus of claim 20, wherein the apparatus is configured such that the first circuit is capable of being communicatively coupled to the single memory bus which is associated with a DDR protocol, the NAND flash memory is the first memory, and the embedded dynamic access memory is the second memory.
 22. The apparatus of claim 20, wherein the apparatus is configured such that the second circuit includes the dynamic random access memory.
 23. The apparatus of claim 20, wherein the apparatus is configured for, in connection with one or more of the multiple instructions, translating a first protocol associated with the single memory bus into a second protocol associated with at least one of the first additional memory bus or the second additional memory bus.
 24. The apparatus of claim 20, wherein the apparatus is configured for emulating an appearance that only a single memory class is present.
 25. The apparatus of claim 20, wherein the apparatus is configured for emulating an appearance that a different memory class is present.
 26. The apparatus of claim 20, wherein the apparatus is configured such that at least one of the first circuit or the second circuit provides compatibility between two signals.
 27. The apparatus of claim 1, wherein the apparatus is configured for executing a plurality of threads in connection with the first memory, and fetching one or more pages from the second memory using a time between the execution of the plurality of threads.
 28. The apparatus of claim 27, wherein the apparatus is configured such that the fetching the one or more pages includes moving particular data between the first memory and the second memory.
 29. The apparatus of claim 27, wherein the apparatus is configured such that the fetching the one or more pages includes transferring particular data between the first memory and the second memory.
 30. The apparatus of claim 27, wherein the apparatus is configured such that the fetching the one or more pages includes retrieving particular data.
 31. The apparatus of claim 27, wherein the apparatus is configured such that the fetching the one or more pages includes issuing a command.
 32. The apparatus of claim 27, wherein the apparatus is configured such that the fetching of pages is performed in hardware and software.
 33. The apparatus of claim 27, wherein the apparatus is configured such that the executing of at least one of the plurality of threads in connection with the first memory, involves the first operation and the second operation.
 34. The apparatus of claim 1, wherein the apparatus further includes a third memory, and the third memory is communicatively coupled to the second memory.
 35. The apparatus of claim 34, wherein the first memory class includes flash memory, the second memory class includes dynamic random access memory.
 36. The apparatus of claim 1, wherein the apparatus further includes a third memory, the third memory communicatively coupled to at least one of the first memory or the second memory.
 37. The apparatus of claim 36, wherein the apparatus is configured such that the third memory is of a third memory class.
 38. The apparatus of claim 36, wherein the apparatus is configured such that the first memory includes NAND flash memory, the second memory includes embedded dynamic random access memory for serving as at least one of a temporary store or a de-staging mechanism, and the third memory includes dynamic random access memory for serving as a buffer.
 39. The apparatus of claim 36, wherein the apparatus is configured such that receiving at least one of the multiple instructions via the single memory bus, results in a third operation on at least a portion of the data in connection with the third memory.
 40. The apparatus of claim 1, wherein the apparatus is configured for receiving a first read command in connection with particular data, and issuing a second read command in connection with the particular data in response to the first read command.
 41. The apparatus of claim 40, wherein the apparatus is configured such that the first read command is standard and is capable of being received from an operating system by a driver utilizing a first speed; and the second read command is non-standard and is issued by the driver to the physical memory sub-system utilizing a second speed via the single memory bus.
 42. The apparatus of claim 1, and further comprising the single memory bus.
 43. The apparatus of claim 42, wherein the single memory bus includes at least two of a command bus, an address bus, a data bus, and a control bus.
 44. The apparatus of claim 42, wherein the single memory bus includes a command or control bus; an address bus; and a data bus.
 45. The apparatus of claim 1, wherein the apparatus is configured such that the instruction is of a same type as the another instruction.
 46. The apparatus of claim 1, wherein the apparatus is configured such that the instruction is of a different type from the another instruction.
 47. The apparatus of claim 1, wherein at least one additional memory bus is included via which at least one of the first memory or the second memory is incapable of receiving the multiple instructions.
 48. The apparatus of claim 1, wherein the apparatus is configured such that the first operation includes a read operation.
 49. The apparatus of claim 1, wherein the apparatus is configured such that the second operation includes a copy or transfer operation.
 50. The apparatus of claim 1, wherein the apparatus is configured such that the at least portion of the data includes an entirety of the data.
 51. The apparatus of claim 1, wherein the apparatus is configured such that the data includes a page.
 52. The apparatus of claim 1, wherein the apparatus is configured such that the data includes a single portion of a page.
 53. The apparatus of claim 1, wherein the apparatus is configured such that the status indicates that the at least portion of the data is stored in the second memory.
 54. The apparatus of claim 1, wherein the apparatus is configured such that the instruction is a standard instruction that results in at least one non-standard instruction that: results in the first operation that includes a read operation for reading the at least portion of the data from the first memory, and further results in the second operation that is for placing the at least portion of the data in the second memory.
 55. The apparatus of claim 54, wherein the apparatus is configured such that the non-standard instruction includes a Cache Miss instruction.
 56. The apparatus of claim 54, wherein the apparatus is configured such that the non-standard instruction includes a special instruction.
 57. The apparatus of claim 54, wherein the apparatus is configured such that the non-standard instruction includes special data.
 58. The apparatus of claim 54, wherein the apparatus is configured such the physical memory sub-system requires the multiple instructions because the apparatus is configured for emulating an appearance that a different memory class is present.
 59. The apparatus of claim 54, wherein the apparatus is configured such the physical memory sub-system requires the multiple instructions because the apparatus is configured for emulating an appearance that only a single memory class is present.
 60. The apparatus of claim 1, wherein the apparatus is configured such that the first memory and the second memory are hierarchically coupled.
 61. A system comprising the apparatus of claim 1, and further comprising a computer program product including code for cooperating with the apparatus such that the first memory and the second memory are capable of receiving the multiple instructions via the single memory bus.
 62. A system comprising the apparatus of claim 1, and further comprising a central processing unit for cooperating with the apparatus such that the first memory and the second memory are capable of receiving the multiple instructions via the single memory bus.
 63. The apparatus of claim 1, wherein the apparatus is configured such that at least one of the multiple instructions includes at least one of a copy command, a read command, or a write command.
 64. The apparatus of claim 1, wherein the apparatus is configured such that the random access data read is performed on the fly.
 65. The apparatus of claim 1, wherein the apparatus is configured such that the random access data read is one of a plurality of random access reads interspersed with a plurality of random access writes performed in real-time.
 66. The apparatus of claim 1, wherein the apparatus is configured such that the random access data read is performed for non-backup purposes.
 67. The apparatus of claim 1, wherein the apparatus is configured such that the random access includes an arbitrary access.
 68. The apparatus of claim 1, wherein the apparatus is configured such that the random access includes an access in connection with at least one of an arbitrary time or an arbitrary address.
 69. The apparatus of claim 1, wherein the apparatus is configured such that the random access includes a burst random access.
 70. The apparatus of claim 1, wherein the apparatus is configured such that a SATA bus is communicatively coupled between the first memory and the second memory.
 71. The apparatus of claim 1, wherein the apparatus is configured such that the status includes a status message.
 72. The apparatus of claim 1, wherein the apparatus is configured such that the status is provided by being made accessible to a source of the multiple instructions.
 73. The apparatus of claim 1, wherein the apparatus is configured such that the status is provided by being made accessible to a central processing unit from which the multiple instructions are received.
 74. The apparatus of claim 1, wherein the apparatus is configured such that the multiple instructions are received via the single memory bus, and other instructions are communicated via another memory bus.
 75. The apparatus of claim 1, wherein the apparatus is configured such that the multiple instructions include the instruction, the another instruction, and yet another instruction.
 76. The apparatus of claim 1, wherein the apparatus is configured such that the instruction and the another instruction each include read instructions.
 77. The apparatus of claim 1, wherein the apparatus is configured such that at least one of the first operation, the second operation, or the status results from receiving the instruction, utilizing at least one additional instruction.
 78. The apparatus of claim 1, wherein the apparatus is configured such that at least one additional operation exists between at least two of the first operation, the second operation, and the status.
 79. The apparatus of claim 1, wherein the apparatus is configured such that the first operation occurs before the second operation, and the second operation occurs before the status being provided. 